Enable XOR Logic Circuit Using Transmission-Gate Substitutes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current logic gate implementations, particularly in semiconductor devices, face inefficiencies in terms of transistor count and power consumption due to the complexity of Boolean functions and the need for minimization techniques like switch minimization to reduce the number of transistors and gates while maintaining functionality.
Innovation Solution
The approach involves generating macro standard cells by rearranging elementary standard cells using automatic placement and routing to optimize area and transistor count, implementing logic circuits for functions like enable XOR and EXNR using combinations of OR-AND-Invert and AND-OR-Invert circuits, and optimizing transistor configurations for reduced power consumption and improved driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If standard logic gate implementations are used, then functionality is maintained, but transistor count and power consumption increase
Solution Approach 1:
The patent merges multiple logic gates into composite logic gates that perform multiple Boolean functions simultaneously. For example, a single composite logic gate integrates the functionality of multiple elementary logic gates, reducing the overall transistor count and power consumption while maintaining the required logical operations.
Solution Approach 2:
The composite logic gates are designed to be universal, capable of performing multiple different Boolean functions depending on the configuration of their inputs and internal transistor arrangements. This multi-functionality allows a single gate structure to replace several specialized gates, thereby reducing the total number of transistors and power consumption.
2Loss of energy
If composite logic gates are designed to reduce transistor count, then power consumption decreases, but design complexity increases
Solution Approach 1:
The design process is segmented into systematic steps: selecting target Boolean functions, determining optimal transistor configurations, and verifying functionality. This segmentation breaks down the complex design task into manageable components, reducing the perceived complexity while achieving power consumption reductions through optimized transistor arrangements.
Solution Approach 2:
The patent systematically varies transistor parameters such as switching thresholds, channel widths, and lengths to optimize the performance of composite logic gates. By changing these parameters, the design achieves reduced power consumption while maintaining functionality, and the systematic approach to parameter optimization reduces design complexity through methodical exploration rather than trial-and-error.
Data Source
AI summary
A logic circuit including first and second inverters, first and second NAND circuits, a transmission gate, and a transmission-gate-substitute (TGS) circuit, and wherein: for each of the first and second NAND circuits, a first input is configured to receive corresponding first and second data signals, and a second input is configured to receive an enable signal; the first inverter is configured to receive an output of the first NAND circuit; the transmission gate and the TGS circuit are arranged as a combination circuit which is configured to receive an output of the second NAND circuit as a data input, and outputs of the first inverter and the second NAND circuit as control inputs; the second inverter is configured to receive an output of the combination circuit; and an output of the second inverter represents one of an enable XOR (EXOR) function or an enable XNR (EXNR) function.