Encapsulated Semiconductor Package Layout for Accurate Die Stacking

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Solution Overview

Problem

The semiconductor industry faces challenges in miniaturization and packaging techniques as demand increases for smaller, faster, and lower power consumption devices, with existing bonding processes being complex and in need of improvement for stacked semiconductor devices.

Innovation Solution

A semiconductor package system and method involving the formation of a first and second die within a wafer, with a protective layer, singulation, encapsulation, and the use of seed layers, redistribution layers, and through vias to facilitate electrical connections and separation, enabling efficient packaging of stacked semiconductor devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If repeated reductions in minimum feature size are used to improve integration density, then more components can be integrated into a given area, but the physical size of the semiconductor device increases

Engineering Contradiction:
Improveintegration densityVSAvoidphysical size
Core Design Contradiction:
Quantity of substanceVSVolume of moving object

Solution Approach 1:

The patent transitions from planar (2D) integration to three-dimensional (3D) stacked integration. Multiple semiconductor dies are bonded vertically to form stacks, utilizing the vertical dimension to increase integration density without proportionally increasing the device footprint. This dimensional change allows more functional components to be packed into a smaller overall volume.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a hierarchical nesting structure where multiple dies are stacked and enclosed within an encapsulant. The encapsulant acts as a container that houses the stacked dies, interconnect structures, and other components, creating a compact nested arrangement that maximizes space utilization and reduces overall device size.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If sophisticated bonding techniques are used to create stacked semiconductor devices, then functional integration is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvefunctional integrationVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the semiconductor manufacturing process into separate stages: die fabrication, die stacking/bonding, and encapsulation. This segmentation allows each stage to be optimized independently and enables parallel processing of multiple dies before stacking, thereby reducing overall manufacturing complexity while maintaining functional integration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by fabricating and preparing multiple dies separately before the stacking process. Contact bumps and interconnect structures are formed on the dies in advance, and dies are pre-assembled into stacks before final encapsulation. This preliminary preparation simplifies the main bonding process and improves manufacturing efficiency.

Inventive Principle:
Principle #10Preliminary action

3Volume of moving object

If stacked and bonded semiconductor devices are used to reduce physical size, then device miniaturization is achieved, but bonding accuracy requirements increase

Engineering Contradiction:
Improvedevice sizeVSAvoidbonding accuracy
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent introduces an encapsulant as an intermediary material that bonds the stacked dies together and provides mechanical support. The encapsulant fills voids between dies, compensates for minor misalignments, and distributes mechanical stresses, thereby reducing the stringency of bonding accuracy requirements while achieving compact device size.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs parameter changes in the bonding process, including controlled temperature, pressure, and bonding time, to achieve reliable die-to-die and die-to-substrate bonding. By optimizing these parameters, the process becomes more tolerant of variations in die alignment and surface flatness, reducing the need for extremely high bonding accuracy.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11901319B2Semiconductor package system and method
Publication Date: 2024.02.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11901319B2 patent drawing
  • US11901319B2 patent drawing
  • US11901319B2 patent drawing

AI summary

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.