Encapsulated Metal Interconnects via Self-Aligned Etch Stop
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Solution Overview
Problem
As integrated circuit technology scales down, the complexity of back-end connections increases, leading to challenges in alignment of photolithography masks, electromigration, and time-dependent dielectric breakdown due to smaller and closer vias and metal lines.
Innovation Solution
A method is introduced where first and second dielectric layers are selectively etchable with respect to a protective dielectric covering, allowing for the formation of contact vias to metal tracks with large mask features, followed by deposition and planarization of conductive material to form integral metal tracks, encapsulating them in a high-density dielectric layer to prevent electromigration and breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If photolithography masks are used with smaller features to create smaller interconnection features, then interconnection size is reduced, but alignment difficulty increases
Solution Approach 1:
The patent introduces a self-aligned etch stop layer as an intermediary between the photolithography mask and the underlying dielectric layers. This layer automatically defines the etching boundaries, eliminating the need for precise mask alignment. The etch stop layer is positioned between the interlevel dielectric and the underlying structure, serving as a physical barrier that stops the etch process automatically, thus resolving the alignment precision problem while maintaining small interconnection features.
2Quantity of substance
If vias and metal lines are made smaller and closer together to scale down technology, then device density increases, but electromigration and time dependent dielectric breakdown increase
Solution Approach 1:
The patent applies different material properties to different regions of the interconnection structure. Specifically, it uses a self-aligned etch stop layer with distinct etch selectivity in critical regions where vias connect to metal lines. This creates locally optimized structures where the etch stop layer provides enhanced protection and definition at via interfaces, improving reliability against electromigration and dielectric breakdown while maintaining high device density through compact routing.
3Length of moving object
If complex patterning schemes such as double patterning are used to create smaller interconnection features, then interconnection size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs a self-aligned etch stop layer that automatically defines the patterning boundaries without requiring additional photolithography steps. The etch stop layer is positioned and dimensioned to self-align with the via openings, enabling the etch process to automatically create precisely sized interconnection features. This self-service mechanism eliminates the need for complex double patterning schemes, reducing manufacturing complexity while achieving small interconnection dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables precise and reliable formation of metal interconnections with reduced alignment requirements, improved resistance to electromigration, and protection against time-dependent dielectric breakdown, enhancing the performance and reliability of integrated circuits.
Implementation Method 1
the protective covering on the second metal tracks acts as a mask to form the vias because the protective covering is not etched by the etchant that opens the vias
Implementation Method 2
The first and second dielectric layers are selectively etchable with respect to the protective dielectric covering
Implementation Method 3
A conductive material is then deposited in the vias and over the second dielectric layer and protective layer
Data Source
AI summary
A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.