Encapsulated Semiconductor Package With Laser-Ablated Redistribution Vias

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Solution Overview

Problem

Existing semiconductor packaging techniques face challenges in reducing interconnect densities and increasing design flexibility, particularly in stacking grid arrays and incorporating metal shield caps without additional through vias.

Innovation Solution

A method involving laser-ablation of via holes through encapsulation, deposition of conductive material to form blind vias, and creation of multiple buildup dielectric layers with laser-ablated artifacts filled with metal to form conductive patterns, allowing for flexible redistribution of terminals and integration of metal shield caps without additional vias.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through vias are used to connect metal shield cap to ground terminal, then electrical connection is achieved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidvia structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the electrical connection function from the traditional through-via structure and relocates it to the bottom surface of the substrate. Ground terminals are directly formed on the bottom surface, eliminating the need for through vias to connect the metal shield cap to ground, thereby reducing device complexity while maintaining electrical connectivity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a vertical connection approach (through vias penetrating the substrate) to a horizontal/surface-level connection approach (ground terminals on the bottom surface). This dimensional shift allows the metal shield cap to be connected to ground without requiring depth-intensive via structures, simplifying the overall device architecture

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If interconnect density is increased to accommodate stacking requirements, then component integration is improved, but design flexibility and manufacturing ease deteriorate

Engineering Contradiction:
Improvecomponent stackingVSAvoidinterconnect density
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent segments the interconnect structure into distinct functional zones: signal interconnects for component stacking and ground terminals for shielding. This segmentation allows independent optimization of each function, enabling component stacking without requiring high overall interconnect density, thus maintaining ease of manufacture

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by providing ground terminals specifically where needed for the metal shield cap connection, rather than uniformly distributing interconnects throughout the substrate. This localized approach enables stacking functionality where required while keeping the overall interconnect density low, preserving manufacturing simplicity

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces interconnect densities, enhances design flexibility, and enables the stacking of components while providing a metal shield cap without the need for additional through vias, improving the overall efficiency and functionality of semiconductor packages.

Implementation Method 1

Via holes are laser-ablated through the encapsulation

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Implementation Method 2

Laser-ablated artifacts are laser-ablated in the first buildup dielectric layer

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Data Source

PatentUS11848214B2Encapsulated semiconductor package
Publication Date: 2023.12.19 AMKOR TECH SINGAPORE HLDG PTE LTD
  • US11848214B2 patent drawing
  • US11848214B2 patent drawing
  • US11848214B2 patent drawing

AI summary

A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.