Multi-Level Cell Memory Using Enclosed Charge Trapping
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Solution Overview
Problem
Conventional silicon-based non-volatile memories have complex fabrication processes and high processing temperatures, making them unsuitable for next-generation system-on-panels and flexible transparent electronic devices, and they struggle to improve storage density effectively.
Innovation Solution
A multi-level cell thin-film transistor memory structure is developed, comprising a gate electrode, charge blocking layer, charge trapping layer fully enclosed by a charge tunneling layer, active region, and source/drain electrodes, using materials like ZnO, In2O3, and IGZO, fabricated using techniques such as atomic layer deposition and magnetic sputtering, allowing for low-temperature processing and multi-level cell storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional silicon-based non-volatile memories are used, then storage density can be improved by downsizing devices, but fabrication process complexity and processing temperature increase significantly
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based semiconductors to a-IGZO (amorphous indium gallium zinc oxide) semiconductors, which enables low-temperature fabrication processes while maintaining or improving storage density. This material substitution fundamentally alters the fabrication temperature parameter from high to low range, resolving the contradiction between storage density improvement and process complexity.
Solution Approach 2:
The patent replaces complex ion injection or doping mechanisms with a simpler fabrication approach using a-IGZO semiconductor channels. The new material system inherently provides the necessary electrical properties without requiring complex doping processes, thus reducing fabrication process complexity while achieving high storage density through multi-level cell implementation.
2Quantity of substance
If conventional silicon-based non-volatile memories are used, then storage density can be improved by increasing the number of devices in unit area, but processing temperature becomes unacceptably high
Solution Approach 1:
The patent fundamentally changes the temperature parameter by adopting a-IGZO semiconductor materials that enable fabrication at low temperatures (typically below 200°C). This material parameter change allows for high storage density implementation without the penalty of high processing temperatures, as the a-IGZO material system inherently supports low-temperature processing while maintaining device performance.
Solution Approach 2:
The patent employs composite material structures including a-IGZO semiconductor channels combined with appropriate dielectric and electrode materials. This composite approach enables the achievement of high storage density through multi-level cell architecture while the a-IGZO component ensures low-temperature processing compatibility, resolving the temperature-density contradiction.
3Ease of manufacture
If charge trapping layer is exposed to ambient environment, then fabrication process is simpler, but data retention property and memory performance stability deteriorate
Solution Approach 1:
The patent implements a nested structure where the charge trapping layer is completely enclosed within the charge tunneling layer, forming a protective capsule-like configuration. This nesting arrangement protects the charge trapping layer from ambient environment exposure, ensuring data retention and performance stability while maintaining fabrication simplicity through conformal deposition processes that naturally create the enclosed structure.
Solution Approach 2:
The patent uses thin film structures where the charge tunneling layer forms a protective shell around the charge trapping layer. This thin film encapsulation isolates the charge trapping layer from the ambient environment, preventing degradation and maintaining reliability, while the thin film nature allows for low-temperature fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances data retention and memory performance stability by isolating the charge trapping layer, improves storage density through multi-level cell functionality, and reduces thermal budget, making it compatible with thin-film transistor processes and suitable for flexible transparent devices.
Implementation Method 1
the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience
Implementation Method 2
a charge trapping layer, a charge tunneling layer... a material of the charge trapping layer is any one of ZnO, In2O3, Ga2O3, SnO2, InSnO, or IGZO
Implementation Method 3
a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes
Data Source
AI summary
A multi-level cell thin-film transistor memory and a method of fabricating the same, a structure of which memory comprises sequentially from down to top: a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes; wherein the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience, which prevents change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment, reduces loss of charges stored in the charge trapping layer, and enhances data retention property and device performance stability; a metal oxide semiconductor thin film is utilized as the charge trapping layer of the memory, which implements multi-level cell storage and improves storage density.