Encoded Address Routing for Dense IC Interconnect Layouts
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Solution Overview
Problem
The increasing number of transistors in integrated circuits (ICs) leads to increased interconnect congestion, which affects the efficiency of routing and can result in interference and crosstalk among address lines, limiting the interconnect density and increasing the spacing between metal traces.
Innovation Solution
The implementation of address encoding using an encoder to reduce the number of address lines and subsequent decoding by a decoder, which reduces routing congestion by using fewer interconnects and allowing for smaller feature sizes, thereby improving interconnect density and reducing interference and crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of transistors and metal layers is increased to provide more interconnect, then the interconnect density increases, but routing congestion and interference among address lines worsen
Solution Approach 1:
The patent applies parameter changes by encoding address lines to reduce their number. Instead of routing all address lines directly, the system encodes them into fewer lines, changing the parameter of address line quantity from N to log2(N). This reduces routing congestion and interference while maintaining the ability to address all required locations, effectively resolving the contradiction between interconnect density and harmful interference effects.
2Device complexity
If address lines are routed directly without encoding, then the routing is simple, but the number of interconnects required increases leading to routing congestion
Solution Approach 1:
The patent applies segmentation by dividing the address routing function into three distinct segments: encoding circuitry that converts N address lines into log2(N) encoded lines, routing interconnects that carry the encoded signals, and decoding circuitry that converts the encoded lines back to N address lines. This segmentation reduces the number of interconnects required in the routing segment while maintaining full addressing capability through the encoding/decoding process.
3Productivity
If more metal layers are used to accommodate increased transistors, then the interconnect capacity increases, but the spacing between metal traces must increase reducing manufacturing efficiency
Solution Approach 1:
The patent applies parameter changes by transforming the address line parameter from N unencoded lines to log2(N) encoded lines. This parameter transformation reduces the number of metal traces required, allowing for smaller spacing between traces and improved manufacturing efficiency. The encoding process enables the same addressing capability with fewer physical interconnects, directly addressing the spacing and productivity contradiction.
Data Source
AI summary
An integrated circuit (IC) includes a circuit, an encoder, and a decoder. The circuit is coupled to circuitry in the IC via a first set of interconnect fabricated using a metal layer. The encoder encodes a plurality of address lines to provide a plurality of encoded address lines. The decoder decodes the plurality of address lines. The plurality of encoded address lines are routed using a second set of interconnect fabricated using the metal layer.