Encoded Bit Inversion for Reliable Low-Power Asymmetric Memory
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Solution Overview
Problem
Current memory technologies face challenges in reliability and power consumption, particularly in asymmetric memories like MRAM and R-RAM, where stuck-at faults and power consumption vary significantly between writing 0 and 1, and existing data storage methods do not effectively address these issues.
Innovation Solution
The proposed solution involves an apparatus and method that uses data inversion techniques, employing a processing unit to encode bits using a linear error correcting code and determine an inversion decision to either store bits directly or invert them, thereby adapting to the specific fault patterns and energy requirements of the memory type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored directly without inversion in asymmetric memories, then the storage process is simple, but reliability deteriorates due to stuck-at faults and unidirectional errors
Solution Approach 1:
The patent applies data inversion by determining whether to invert subsets of encoded bits before storage based on error patterns. When unidirectional errors or stuck-at faults are detected, the system inverts the data (changing 0s to 1s and vice versa) to mask these errors. This inversion strategy directly addresses reliability issues in asymmetric memories by transforming the data representation to compensate for systematic errors.
Solution Approach 2:
The patent employs preliminary error detection and inversion decision-making before data storage. The processing unit encodes data with error correcting codes, detects potential error patterns, and determines inversion decisions prior to writing data to memory. This preliminary action prevents errors from being stored in the first place, improving reliability without requiring complex post-storage correction mechanisms.
2Reliability
If data inversion is applied to mask faults, then reliability improves, but power consumption increases due to additional processing operations
Solution Approach 1:
The patent applies local quality by inverting only specific subsets of bits rather than the entire data word. The system divides encoded data into subsets and applies inversion selectively based on detected error patterns. This localized approach reduces the computational overhead and power consumption compared to inverting all bits, while still effectively masking the relevant errors in the affected subsets.
Solution Approach 2:
The patent changes the parameter of data representation by inverting bit values (0 to 1, 1 to 0) based on detected error conditions. This parameter change transforms the data to mask errors while requiring minimal processing energy, as inversion is a simple bitwise operation rather than a complex transformation.
3Reliability
If error correcting codes with code distance at least 3 are used, then error correction capability improves, but device complexity increases due to encoding and decoding operations
Solution Approach 1:
The patent applies partial action by using error correcting codes with code distance at least 3, which provides correction capability for up to 1 error per codeword. This level of correction is sufficient for many applications without requiring the more complex overhead of higher-distance codes. The system balances error correction capability with acceptable coding complexity by selecting the minimum necessary code distance.
4Reliability
If subsets of encoded bits are inverted based on error patterns, then error masking improves, but processing time increases due to inversion decision-making
Solution Approach 1:
The patent performs inversion decision-making as a preliminary action during the data writing process rather than during reading or later processing. The system determines whether to invert subsets of bits before data is stored in memory, which prevents errors from being stored in the first place. This timing optimization reduces overall processing time compared to performing inversion decisions after data retrieval.
Data Source
AI summary
An apparatus includes a processing unit and a memory. The processing unit is configured to encode a plurality of bits to obtain a plurality of encoded bits, the processing unit is configured to determine an inversion decision. When the inversion decision indicates that the subset of the encoded bits shall not be inverted, the processing unit is configured to store, as a stored word, bits of the first codeword into the memory. When the inversion decision indicates that the subset of the encoded bits shall be inverted, the processing unit is configured to invert each encoded bit of a subset of the encoded bits to obtain a second codeword and to store the second codeword into the memory.