Encoded Chip Select for High-Rank Memory Systems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory systems are limited in supporting multiple memory ranks per channel due to the restriction of chip select lines, which prevents the simultaneous access of more than four ranks on a DIMM, necessitating additional pins and complex logic to manage higher rank DIMMs like eight-rank DIMMs.
Innovation Solution
The implementation of a legacy encoder that encodes chip select signals into a multi-bit word with fewer bits than the number of ranks, allowing for the selection and communication of multiple ranks using existing four CS pins, enabling support for up to 2N ranks by using encoded four-bit words with one or more active bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional chip select lines are used with one pin per rank, then each rank can be uniquely selected, but the number of supported ranks is limited to the number of available pins (four ranks maximum)
Solution Approach 1:
The patent changes the parameter representation by encoding rank selections using multi-bit words instead of single-bit signals. Each chip select line transmits a multi-bit encoded value that identifies a subset of ranks, allowing four chip select lines to address up to 16 ranks (2^4 combinations) instead of just four ranks.
Solution Approach 2:
The patent transitions from a one-dimensional mapping (one pin per rank) to a multi-dimensional encoding scheme where each pin carries multiple bits of information. This dimensional change in signal representation allows the same physical pins to control a larger number of ranks through combinatorial encoding.
2Adaptability or versatility
If additional chip select pins are added to support more than four ranks, then more ranks can be addressed, but the hardware complexity and pin requirements increase
Solution Approach 1:
The patent makes the existing four chip select pins universal by enabling them to address multiple rank configurations (up to 16 ranks) through encoding. The same pins that previously could only address four ranks now serve multiple functions by transmitting encoded subset selections, eliminating the need for additional pins.
Solution Approach 2:
The patent uses encoded representations (multi-bit words) that copy and compress the rank selection information. Instead of requiring a unique physical pin for each rank, the system uses compressed encoded copies of rank identifiers that can be transmitted through the existing pin infrastructure.
3Adaptability or versatility
If encoded chip select signals are used to support more ranks, then the number of supported ranks increases without additional pins, but the signal encoding and decoding complexity increases
Solution Approach 1:
The patent segments the rank selection problem into two parts: encoding at the controller side and decoding at the memory module side. The encoding logic converts rank selections into multi-bit subset identifiers, while the decoding logic on the memory module interprets these codes to activate the appropriate ranks. This segmentation distributes the complexity between controller and memory module.
Data Source
AI summary
Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written.