Encoded Master Clock Transmission for Audio Sync and Messaging
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Solution Overview
Problem
Existing audio devices in a system struggle with synchronizing clock signals due to latency across channels, necessitating specific data transmission protocols like AES/EBU or SPDIF, which restrict flexibility.
Innovation Solution
A transmitter generates an encoded clock signal with adjustable edge timings based on bit values, allowing simultaneous transmission of clock timing and message without relying on specific protocols, using a pseudorandom number generator to encode data streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a master clock is employed to synchronise audio devices, then synchronisation is achieved, but latency across channels causes misalignment of clock pulses between devices
Solution Approach 1:
The transmitter preliminarily encodes timing information and device identification data into the clock signal itself before transmission. By embedding this information in advance within the clock pulses, the receiver can immediately decode and adjust for latency without requiring separate synchronization messages or protocols.
Solution Approach 2:
The patent introduces an encoded data stream as an intermediary carrier that conveys both timing information and device identity within the clock signal structure. This intermediary encoding mechanism allows the clock signal to simultaneously serve as both timing reference and data transmission medium, resolving the latency issue by making timing information self-contained.
2Ease of manufacture
If specific data transmission protocols like AES/EBU or SPDIF are used, then data transmission is standardized, but the audio device is tied to using a particular transmission method reducing flexibility
Solution Approach 1:
The clock signal is designed to perform multiple functions simultaneously: it serves as the timing reference for audio sampling, carries device identification information, transmits timing correction data, and enables synchronization without requiring separate protocol layers. This multi-functionality eliminates dependency on proprietary protocols while maintaining standardization benefits.
Solution Approach 2:
The patent merges the data transmission function with the clock signal transmission function. By combining timing information, device identity, and synchronization data into a single encoded clock signal stream, the system eliminates the need for separate data transmission protocols, thereby achieving both standardization and flexibility.
3Device complexity
If clock signals are transmitted without encoding, then transmission is simple, but timing information and messages cannot be transmitted simultaneously
Solution Approach 1:
The encoding scheme utilizes the periodic nature of clock pulses to convey information. Each clock pulse or group of pulses is modulated with encoded data bits, allowing timing information and messages to be transmitted simultaneously through the periodic clock signal structure without requiring continuous separate data streams.
Solution Approach 2:
The patent changes parameters of the clock signal itself (such as pulse width, inter-pulse intervals, or amplitude levels) to encode data information. By modulating these parameters, the clock signal carries both timing reference information and encoded messages, maintaining relative simplicity while enabling simultaneous information transmission.
Data Source
AI summary
The subject-matter of the present disclosure provides a transmitter for a master clock of an audio system. The transmitter comprises an input configured to receive a message to be sent to a receiver of an audio device of the audio system and clock frequency information of a clock signal for synchronising the audio device; a data stream generator configured to determine a data stream based on the message; a pulse shaper configured to generate an encoded clock signal in the form of a rectangular wave having an initiating edge timing based on the clock frequency and a terminating edge timing being earlier than or later than a half cycle of the encoded clock signal depending on a bit value of the data stream; and an output configured to transmit the encoded clock signal to the receiver.