Encoded Full Visibility Data for Memory Testing
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Solution Overview
Problem
Conventional methods for testing semiconductor memory devices are time-consuming and resource-intensive, particularly when identifying defective column planes and bits, as they require full visibility data to correct single-bit errors, which involves substantial data transfer and processing.
Innovation Solution
The implementation of encoded full visibility data generation and encoding test data to enable single-bit forgiveness, allowing for reduced testing time and data transfer by using error correction codes (ECC) to identify and correct single-bit failures, while also detecting multi-bit failures and identifying specific defective bits or column planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional testing methods are used to identify defective column planes and bits, then measurement precision is improved, but testing time and data transfer increase substantially
Solution Approach 1:
The patent extracts only the necessary test data (column address and pass/fail status) from the complete memory array, rather than transferring all test data. By taking out only the essential information needed for defective bit identification, the system achieves accurate defect localization while dramatically reducing data transfer volume and testing time.
Solution Approach 2:
Instead of testing each bit individually and identifying defects through exhaustive data collection, the patent inverts the approach by testing column planes as groups and using the results to indirectly identify defective bits. This inversion reduces the testing burden from individual bit level to column plane level, significantly reducing testing time while maintaining identification accuracy.
2Reliability
If full visibility data is used to correct single-bit errors, then reliability is improved, but data transfer and processing resources increase substantially
Solution Approach 1:
The patent extracts only the essential information needed for error correction (column address and pass/fail status) from the complete test data set. By taking out only the necessary data elements required for single-bit error correction, the system maintains full error correction capability while reducing data transfer volume to a minimum essential level.
Solution Approach 2:
The patent applies partial action by implementing error correction only for single-bit errors rather than attempting to correct all possible error types. This selective approach provides sufficient reliability for single-bit errors while avoiding the excessive data processing required for comprehensive multi-bit error correction, thus reducing data transfer and processing resources.
3Productivity
If encoded full visibility data generation is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory array into multiple column planes, each tested independently. By segmenting the large memory array into smaller manageable column planes, the system can process test results more efficiently and generate encoded data in a structured manner, improving productivity while keeping the encoding logic manageable through systematic organization.
Solution Approach 2:
The patent introduces an intermediary encoding circuit that processes raw test results from column planes and converts them into encoded full visibility data. This intermediary layer simplifies the overall system by providing a dedicated component that handles the complexity of data encoding, thereby improving productivity without requiring the entire system to be redesigned with increased complexity.
Data Source
AI summary
Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed.