Encoded PLL Loop Filter Tuning for Frequency Margin and Lock Time

Solution Overview

Problem

Conventional phase-locked loops (PLLs) face challenges in maintaining optimal operating conditions due to changes in the dividing integer N, which affect the loop filter's capacitances and resistances, leading to suboptimal frequency margin and locking time.

Innovation Solution

A PLL with a loop filtering unit that adjusts its elements, specifically capacitors and resistors, based on an encoded input code using a thermometer encoder to optimize the loop filter's configuration, ensuring optimal performance across varying dividing integers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the dividing integer N is changed to adjust the output frequency, then the frequency range is improved, but the loop filter's operating point becomes suboptimal due to fixed element values

Engineering Contradiction:

Improvefrequency rangeVSAvoidfrequency margin

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The loop filter elements are made dynamically adjustable based on the dividing integer N. The capacitor values are switched using multiplexers controlled by the encoded version of N, allowing the loop filter to adapt its time constant to maintain optimal frequency margin across different output frequencies.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The capacitance values of the loop filter capacitors are changed based on the dividing integer N. By encoding N and using the encoded value to control capacitor switching, the system adjusts the loop filter parameters to maintain optimal operating conditions across different frequency ranges.

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If the dividing integer N is changed to adjust the output frequency, then the frequency range is improved, but the locking time becomes suboptimal due to fixed element values

Engineering Contradiction:

Improvefrequency rangeVSAvoidlocking time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The loop filter elements are made dynamically adjustable based on the dividing integer N. The capacitor values are switched using multiplexers controlled by the encoded version of N, allowing the loop filter to adapt its time constant to maintain optimal locking time across different output frequencies.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The capacitance values of the loop filter capacitors are changed based on the dividing integer N. By encoding N and using the encoded value to control capacitor switching, the system adjusts the loop filter parameters to maintain optimal locking time across different frequency ranges.

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If fixed element values are used in the loop filter, then the device complexity is reduced, but the operating condition cannot be optimized for varying dividing integers

Engineering Contradiction:

Improveelement configurationVSAvoidoperating condition adjustment

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The loop filter capacitor is divided into multiple sub-capacitors that can be independently switched. This segmentation allows different capacitance values to be selected based on the dividing integer N, enabling optimization of operating conditions without requiring a completely different filter design.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The loop filter elements are made dynamically adjustable based on the dividing integer N. The capacitor values are switched using multiplexers controlled by the encoded version of N, allowing the loop filter to adapt its time constant to maintain optimal frequency margin across different output frequencies.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS7864910B2Phase locked loop

Publication Date: 2011.01.04 SK HYNIX INC

AI summary

A PLL is provided with an optimum operating point in order to have appropriately a frequency margin and a locking time. There is provided a phase looked loop which includes: a frequency divider for dividing an output signal by a dividing integer corresponding to an input code; an encoding unit for encoding the input code to generate an encoded code; and a loop filtering unit configured to adjust elements in response to the encoded code.