Encoded S Gate Layout Using Ancillary Qubits and Domain Walls

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Solution Overview

Problem

The reliable creation and entangling of qubits in quantum computing remains a daunting task.

Innovation Solution

A method is described for performing an encoded S gate on a logical qubit using a port and ancillary portion of a surface code arrangement, involving stabilizer measurements and qubit measurements to generate a domain wall within a bulk region of the encoded S gate, utilizing photonic systems with waveguides and beam splitters to achieve qubit entanglement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If quantum gates are implemented using traditional methods, then quantum computing operations can be performed, but the resource consumption and operational complexity become unmanageably high

Engineering Contradiction:
Improvequantum computing operation efficiencyVSAvoidgate operation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The quantum gate operation is divided into distinct measurement phases (first plurality of stabilizer measurements, second plurality of stabilizer measurements, third plurality of stabilizer measurements) and measurement types (single qubit measurements, dual qubit measurements). This segmentation allows each phase to be optimized independently and reduces the complexity of managing the entire gate operation as a single complex process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Ancillary qubits are introduced as intermediary elements to facilitate the S gate operation. These ancillary qubits serve as mediators between the input logical qubit and the measurement processes, enabling the gate operation to proceed through a structured sequence of measurements rather than requiring direct complex interactions between all computational qubits.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If comprehensive stabilizer measurements are performed to ensure accurate quantum gate operation, then gate reliability improves, but the time and resource consumption increases

Engineering Contradiction:
Improvequantum gate accuracyVSAvoidgate operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The first plurality of stabilizer measurements and first plurality of single qubit measurements are performed before the main computational steps of the S gate. These preliminary measurements prepare the quantum state and establish measurement outcomes that guide subsequent operations, ensuring reliability is built into the gate execution from the beginning rather than requiring extensive verification afterward.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The measurement process continues through multiple phases without interruption - the first plurality of stabilizer measurements flows into the second plurality, which connects to the third plurality. This continuous measurement approach maintains quantum coherence and ensures that each measurement builds upon previous results, achieving high reliability through uninterrupted verification rather than discrete checkpoint validations.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS12488268B1Resource efficient logical quantum gates
Publication Date: 2025.12.02 PSIQUANTUM CORP
  • US12488268B1 patent drawing
  • US12488268B1 patent drawing
  • US12488268B1 patent drawing

AI summary

A method of performing an encoded gate on a logical qubit, wherein the encoded gate includes the port portion and an ancillary portion, and wherein a lower surface of the port portion is coupled to an upper surface of the ancillary portion, includes performing a first plurality of stabilizer measurement on the port portion, performing both single qubit and dual qubit measurements on a plurality regions of the ancillary portion to generate topological features such as a twists, domain walls, and defects within a bulk region of the encoded S gate.