Encoder Bit Allocation Using MSB-LSB Split Coding

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Solution Overview

Problem

Digital communication systems face inefficiency due to non-integer length code words resulting from channel bandwidth constraints, leading to underutilization of bits and increased computational costs in high-bandwidth, high-fidelity systems.

Innovation Solution

The system employs a combination of Factorial Pulse Coding and Arithmetic Coding, where multi-bit code words are split into Most Significant Bits (MSB) and Least Significant Bits (LSB) portions, with Arithmetic Coding applied to MSBs to optimize bit usage and reduce computational complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If k bits are allocated to represent n unique frames where n is not a power of two, then the system can represent all unique frames, but the bits are not fully utilized leading to inefficiency

Engineering Contradiction:
Improvecomplete representation of unique framesVSAvoidbit utilization efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent segments the code word into two distinct parts: MSB (Most Significant Bit) portion and LSB (Least Significant Bit) portion. The MSB portion uses ⌈log2(n)⌉ bits to represent the n unique frames, while the LSB portion uses the remaining bits to represent additional information. This segmentation allows the system to fully utilize all k bits without waste, while still completely representing all n unique frames through the MSB portion.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If traditional integer-length code words are used, then the encoding is simple, but non-integer length code words result from bandwidth constraints leading to computational complexity

Engineering Contradiction:
Improveencoding simplicityVSAvoidbandwidth utilization efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the code word into MSB and LSB portions, where the MSB portion handles the frame identification with ⌈log2(n)⌉ bits and the LSB portion handles additional information. This segmentation enables the system to achieve non-integer effective code length for better bandwidth utilization while maintaining relatively simple encoding procedures through separate handling of the two portions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different coding strategies to different parts of the code word: the MSB portion uses standard integer-length coding for frame identification, while the LSB portion uses the remaining bits for additional information. This local differentiation allows each part to be optimized for its specific purpose, achieving overall efficiency without excessive complexity.

Inventive Principle:
Principle #3Local quality

3Reliability

If high precision multiplication operations are performed to process large numbers of codewords, then high bandwidth and high fidelity are achieved, but computational cost increases

Engineering Contradiction:
Improvehigh fidelityVSAvoidcomputational cost
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the coding process into MSB and LSB portions that can be processed separately and independently. This segmentation allows the system to handle large numbers of codewords more efficiently by processing smaller units in parallel or sequentially, reducing the computational burden of high precision multiplication operations while maintaining high fidelity through the combination of both portions.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8890723B2Encoder that optimizes bit allocation for information sub-parts
Publication Date: 2014.11.18 GOOGLE TECHNOLOGY HOLDINGS LLC
  • US8890723B2 patent drawing
  • US8890723B2 patent drawing
  • US8890723B2 patent drawing

AI summary

A digital information encoder including a divider configured to divide a block of information into a plurality of sub-parts, an initial bit allocator configured to perform an initial allocation of bits to a KTH sub-part of said plurality of sub-parts, a processor configured to compute an estimated number of bits for encoding said KTH sub-part, and a bit allocation adjuster configured to obtain an adjusted bit allocation for said KTH sub-part by adjusting said initial allocation of bits to said KTH sub-part based, at least in part, on said estimated number of bits, wherein the encoder encodes said KTH sub-part using said adjusted bit allocation for said KTH sub-part.