Encoder Logic for Shorter Run-Lengths in High-Speed Links
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Solution Overview
Problem
Existing electronic communication systems face challenges in maintaining effective data transmission over long distances due to long run-length sequences of 0s or 1s, which can lead to detection issues for receivers, especially in high-speed links and challenging connections like backplanes.
Innovation Solution
The implementation of encoder circuits that perform logic operations or scramble bit orders to reduce run-lengths, using techniques such as XOR operations or bit order scrambling, which can be selectively applied to achieve shorter run-lengths and maintain DC balance, thereby improving data transmission reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If data is transmitted over long distances via high-speed links, then communication range is improved, but long run-length sequences of 0s or 1s cause detection issues and increase bit errors
Solution Approach 1:
The patent applies encoding schemes that transform the original data bits into encoded bits with modified parameters. Specifically, the encoding process changes the run-length distribution by combining multiple input bits into fewer output bits according to defined mapping rules, ensuring that the encoded data has shorter maximum run-lengths and better transition density, thereby improving detectability over long distances
2Reliability
If encoding schemes are applied to reduce run-lengths, then detection reliability is improved, but device complexity increases
Solution Approach 1:
The encoder is designed to process data in segmented units (e.g., groups of 4 bits or 5 bits at a time) rather than continuously streaming bits. This segmentation allows the use of lookup tables or pre-defined mapping rules for each segment, simplifying the overall encoding logic while achieving effective run-length control through systematic processing of discrete data units
Data Source
AI summary
An apparatus includes an encoder adapted to encode data bits for transmission via a communication link. The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length of the data bits.