Encoder Segmentation for Power Analysis Resistance
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Solution Overview
Problem
Existing encoders are inefficient in reducing power consumption dependence on input values, leading to increased circuit area and propagation delay, particularly when countermeasures against side channel analysis attacks are applied, such as power analysis attacks.
Innovation Solution
The proposed solution involves generating one-hot or one-cold bits for most significant bits (MSBs) and least significant bits (LSBs) using cross-connections and logical operations, separating the encoding process into two logic groups to encode MSBs and LSBs independently, reducing the number of OR gates required and utilizing high fan-in gates to minimize propagation delay and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing encoder designs are used to protect against power analysis attacks, then security against side channel analysis is improved, but circuit area and propagation delay increase
Solution Approach 1:
The encoder is divided into two separate logic groups: a first logic group that processes MSBs (most significant bits) and a second logic group that processes LSBs (least significant bits). Each group independently encodes its respective bits using cross-connected logic gates, preventing power consumption patterns from revealing information about the entire input value while reducing the complexity of each individual logic group compared to a unified encoder design.
2Reliability
If existing encoder designs are used to protect against power analysis attacks, then security against side channel analysis is improved, but propagation delay increases
Solution Approach 1:
By segmenting the encoding process into two independent logic groups handling MSBs and LSBs separately, the critical path length is reduced. Each logic group processes a subset of bits in parallel, decreasing the overall propagation delay compared to a sequential or monolithic encoding approach while maintaining the security properties needed to resist power analysis attacks.
Solution Approach 2:
Within each logic group, multiple logic gates are merged into a cross-connected configuration where gates share common input and output lines. This merging reduces the total number of gate levels in the critical path, thereby reducing propagation delay, while the cross-connection structure ensures that power consumption remains independent of the input value for security against power analysis attacks.
3Productivity
If existing encoder designs are used, then encoding functionality is provided, but power consumption depends on input values making the encoder vulnerable to power analysis attacks
Solution Approach 1:
Each logic group is designed with specific local properties: the first logic group processes MSBs with cross-connected gates optimized for high-order bits, while the second logic group processes LSBs with similar cross-connected structures. This local optimization ensures that power consumption in each group is independent of its input values, and collectively the entire encoder maintains constant power consumption regardless of the full input value, preventing power analysis attacks while preserving encoding functionality.
Data Source
AI summary
A method of encoding and an encoder are provided. The method includes generating first one-hot bits for most significant bits (MSBs) and second one-hot bits for least significant bits (LSBs) using input one-hot bits; encoding the first one-hot bits to the MSBs and complementary MSBs through a first logical operation using a cross-connection; and encoding the second one-hot bits to the LSBs and complementary LSBs through a second logical operation using a cross-connection. The encoder includes a first bit generator, a first encoder, a second bit generator and a second encoder.