Encoding Circuit Matrix Interleaving for Single FEC Implementation
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Solution Overview
Problem
Existing data processing methods in mobile communications require different Forward Error Correction (FEC) circuits for each link due to varying bit error rates, increasing implementation complexity.
Innovation Solution
A data processing method that uses multiple FEC circuits of the same specification to correct errors in multiple received data streams, achieved by coding an m-order matrix formed by data units from each link before modulation, allowing the same FEC circuit to be used across links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different FEC circuits are configured for different links to correct bit errors, then error correction performance is improved, but implementation complexity increases
Solution Approach 1:
The patent applies universality by designing a single FEC circuit that can handle multiple data streams with different bit error rates. Instead of configuring separate FEC circuits for each link, one FEC circuit is shared across multiple links, reducing implementation complexity while maintaining error correction capability through unified processing of interleaved data streams
Solution Approach 2:
The patent applies segmentation by dividing data streams from multiple links into separate groups that are processed sequentially by the same FEC circuit. The interleaving technique segments the data in time and link dimensions, allowing the single FEC circuit to process different links at different times while maintaining optimal error correction for each link's specific bit error rate characteristics
2Reliability
If multiple FEC circuits of different complexities are used for different links, then bit error rate correction is improved, but system resource consumption increases
Solution Approach 1:
The patent implements universality by using a single FEC circuit to serve multiple links with different bit error rates. The circuit is designed to handle varying error conditions through software-configurable parameters and interleaving techniques, eliminating the need for multiple physical FEC circuits and reducing overall system resource consumption
Solution Approach 2:
The patent applies parameter changes by allowing the FEC circuit's operational parameters to be dynamically adjusted based on the specific link being processed. Through configuration parameters and interleaving depth adjustments, the same hardware circuit can optimize its error correction behavior for different bit error rate conditions across multiple links
Data Source
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AI summary
Embodiments of the present invention disclose a data processing method and a data processing apparatus. The method includes: receiving, by an encoding circuit, m data streams by using m receive ports respectively, where the m data streams include m×m data units, and the m×m data units form an m-order matrix A; keeping, by the encoding circuit, a location of one element in each row in the matrix A unchanged and moving remaining m-1 elements to remaining m-1 rows respectively so as to form an m-order matrix B, where a column number of each element in the remaining m-1 elements in the matrix A before the element is moved equals a column number of the element in the remaining m-1 elements in the matrix B after the element is moved; and sending, by the encoding circuit by using m transmit ports, the m×m elements in the matrix B to m different levels of a PAM circuit respectively for performing modulation.