Hardware Encoding Circuit for Mobile Communication Speed
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Solution Overview
Problem
In mobile communication devices, the processing load for generating encoded data using software increases with the number of bits, hindering communication speed due to the need for multiple cycles of shifting, logical product, and exclusive logical addition processes.
Innovation Solution
An encoding circuit with a data-for-encoding register, a data-for-calculation register, a shifter, a first coefficient register, and an encoding logic circuit that performs logical operations to encode data efficiently, reducing the need for multiple cycles by shifting and calculating data bit by bit, and allowing for selection of coefficients based on instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If encoding is performed using software with multiple cycles of shifting, logical product, and exclusive logical addition processes, then the encoding can be flexibly implemented, but the processing load increases and communication speed deteriorates
Solution Approach 1:
The patent replaces software-based encoding processes with a dedicated hardware encoding circuit. The circuit includes a register for storing input data, a shift register for shifting data bits, logic circuits for performing logical product and exclusive logical addition operations, and an output register for storing encoded data. By hardwiring the encoding logic, the system eliminates the need for multiple software cycles, significantly improving processing speed while maintaining encoding flexibility through configurable circuit design.
2Device complexity
If multiple cycles of processes are used to generate one-bit encoded data, then the encoding can be performed with simple circuitry, but the processing time increases and productivity decreases
Solution Approach 1:
The patent combines multiple encoding operations (shifting, logical product, exclusive logical addition) into a single hardware circuit that processes all operations simultaneously. The circuit includes a register for storing input data, a shift register for shifting data bits, logic circuits for performing logical product and exclusive logical addition operations, and an output register for storing encoded data. By merging these operations into parallel hardware components, the system achieves high-speed encoding without requiring multiple sequential cycles, thus improving productivity while keeping the circuit design relatively simple and modular.
Data Source
AI summary
An encoding circuit is disclosed which comprises: a data-for-encoding storing register that stores n-bit data for encoding; a data-for-calculation storing register that stores m-bit data for calculation generated by shifting the data for encoding; a shifter that shifts the data for encoding stored in the data-for-encoding storing register, and shifts and inputs the shifted data into the data-for-calculation storing register; a first coefficient register that stores m-bit first coefficient data indicating a first coefficient for executing encoding; a first logic circuit that is inputted with the data for calculation stored in the data-for-calculation storing register and the first coefficient data stored in the first coefficient register and outputs the logical product for each bit of the data for calculation and the first coefficient data; and a second logic circuit that is inputted with m-bit data outputted from the first logic circuit and outputs the exclusive logical sum of the m-bit data as the encoded data.