Hardware Encoding Format Conversion Circuit

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Solution Overview

Problem

Current processor technologies require significant time and energy to convert between different encoding formats, such as UTF-8 and UTF-16, especially when processing large data streams like XML, due to the inefficiency of general-purpose assembly instructions which can consume multiple CPU cycles per byte.

Innovation Solution

A hardware processor with dedicated decode and execution circuits that can execute a single instruction to convert multiple bytes or elements of character code values from one encoding format to another simultaneously, utilizing specific opcode formats and operands to manage the conversion process efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If general-purpose assembly instructions are used for encoding format conversion, then the conversion can be performed, but the processing time and energy consumption increase significantly

Engineering Contradiction:

Improveconversion speedVSAvoidenergy consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent replaces general-purpose software assembly instructions with dedicated hardware execution circuits that natively support encoding format conversion operations. This substitution of mechanical/software-based processing with hardware-based processing dramatically reduces both time and energy consumption for conversion operations.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces new instruction formats and encoding format conversion operations that change the fundamental parameters of how conversion is performed - from byte-by-byte software processing to vectorized hardware-accellerated batch processing, fundamentally altering the efficiency characteristics of the conversion operation.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If general-purpose assembly instructions process encoding format conversion, then flexibility is maintained, but processing efficiency decreases due to multiple CPU cycles per byte

Engineering Contradiction:

Improvebytes converted per CPU cycleVSAvoidconversion time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent merges multiple conversion operations into a single hardware execution unit that can process multiple bytes simultaneously through vectorized operations. The execution circuit combines several conversion functions into one unified hardware block that operates in parallel, achieving many bytes converted per CPU cycle instead of one byte per cycle.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from scalar byte-by-byte processing to vectorized parallel processing by introducing vector registers and SIMD-style operations. This dimensional change allows the same conversion logic to operate on multiple data elements simultaneously, dramatically increasing throughput.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Productivity

If dedicated hardware circuits are implemented for encoding format conversion, then processing efficiency improves, but device complexity increases

Engineering Contradiction:

Improveconversion throughputVSAvoidprocessor architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent designs the execution circuit and instruction formats to be multi-functional, supporting multiple encoding format conversions (UTF-8, UTF-16, UTF-32, ASCII) and various data element widths (8-bit, 16-bit, 32-bit) through a single unified hardware structure. This universality reduces the need for separate dedicated circuits for each conversion type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements dynamic configurability in the execution circuit where parameters such as source encoding format, destination encoding format, and vector length can be dynamically specified through instruction operands. This allows the same hardware to adapt to different conversion requirements without physical reconfiguration, managing complexity through software-controlled flexibility.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10146542B2Hardware apparatus and methods for converting encoding formats

Publication Date: 2018.12.04 INTEL CORP

AI summary

Methods and apparatuses relating to converting encoding formats are described. In one embodiment, a hardware processor includes a decode circuit to decode an instruction comprising a state operand, a source vector operand, a destination vector operand, and a control operand, and an execution circuit to execute the instruction to convert elements from the source vector operand in a first encoding format to a second encoding format, store the elements in the second encoding format in the destination vector operand, store a total length of the elements in the second encoding format in the state operand, and set a stream completion indication in the control operand when the elements from the source vector operand are a last elements in a data stream.