Encrypted Cache Line Decryption via Precomputed Masks
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Solution Overview
Problem
Cloud computing environments, where the execution location of code is unknown to users, pose challenges in ensuring code and data confidentiality due to performance impacts from decryption and difficulty in predicting code execution paths, leading to limitations in implementing effective encryption without exposing code to inspection or theft.
Innovation Solution
A method involving encrypting a nonce and count value corresponding to the code or data location in the aggregate code stream, using these values to compute a counter mode mask for near latency-less decryption upon cache miss, ensuring encryption up to the processor's execution unit and reducing the processor's attack surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If code stream encryption is implemented using AES algorithm, then code and data confidentiality is improved, but performance deteriorates due to decryption overhead
Solution Approach 1:
The patent pre-computes counter mode masks for all possible cache line addresses before execution. These masks are stored in a lookup table, so when a cache miss occurs, the decrypted data can be immediately XORed with the pre-computed mask without waiting for decryption. This preliminary preparation eliminates decryption overhead during actual execution.
Solution Approach 2:
The patent divides the code stream into fixed-size cache line segments (e.g., 64 bytes) and encrypts each segment independently using counter mode. Each cache line has its own unique counter value, allowing parallel pre-computation of masks for different segments. This segmentation enables efficient hardware implementation and reduces the complexity of the decryption process.
2Productivity
If code stream is decrypted entirely into memory, then performance is improved by minimizing decryption overhead, but code exposure to malware and operating systems increases
Solution Approach 1:
The patent implements encryption at the cache line level rather than decrypting the entire code stream. Only the specific cache lines that are currently needed for execution are decrypted and immediately processed. This localized approach ensures that minimal code is exposed in plaintext at any given time, reducing the attack surface while maintaining performance.
Solution Approach 2:
The patent introduces an encrypted cache as an intermediary layer between encrypted memory and the processor. The cache stores encrypted cache lines, and a decryption unit translates only the required lines on-demand. This intermediary structure allows the processor to execute code without the operating system or malware having access to the full decrypted code stream in memory.
3Reliability
If decryption is performed for each cache miss, then code confidentiality is maintained, but performance deteriorates due to decryption latency
Solution Approach 1:
The patent pre-computes and stores counter mode masks for all possible cache line addresses in a lookup table during system initialization. When a cache miss occurs, the hardware immediately retrieves the pre-computed mask corresponding to the cache line address and XORs it with the encrypted data. This eliminates the need for time-consuming decryption operations during cache misses, reducing latency to near-zero while maintaining security.
Data Source
AI summary
A method for processing addressable encrypted data representing addressable cleartext data uses an integrated circuit including a processor circuit. The method includes processing the addressable cleartext data in the processor circuit without storing said cleartext data outside the processor circuit.