Encrypted Gate Delay Simulation for IC IP Protection
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Solution Overview
Problem
The existing licensing models for integrated circuits, particularly hard-core licenses, prevent simulation of IP cores, which is essential for accurate signal propagation delay modeling and fault analysis, while soft-core licenses reveal sensitive intellectual property information.
Innovation Solution
The encryption of gate delay information provides pseudo-gate delay values that maintain intellectual property protection while allowing accurate simulation of signal propagation delays, enabling both hard-core and soft-core licensing benefits without revealing actual delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard-core licensing is used to protect intellectual property, then IP protection is improved, but simulation capability deteriorates
Solution Approach 1:
The patent creates encrypted copies of the circuit description that preserve the functional behavior and timing characteristics needed for simulation, while obscuring the actual gate-level implementation details. These encrypted copies allow simulators to operate without revealing sensitive IP information.
Solution Approach 2:
The patent transforms the circuit description into an encrypted format where the parameters are mathematically transformed using encryption functions. The encrypted description maintains the necessary timing and behavioral parameters for simulation while hiding the actual circuit structure through parameter transformation.
2Ease of operation
If soft-core licensing is used to enable simulation, then simulation capability is improved, but IP protection deteriorates
Solution Approach 1:
Instead of providing the original unencrypted circuit description, the system provides an encrypted copy that is functionally equivalent for simulation purposes but cannot be used to reverse-engineer the actual IP implementation. The copy preserves simulation capabilities while preventing IP extraction.
Solution Approach 2:
The encrypted circuit description acts as an intermediary between the IP owner and the simulator. It enables the simulator to access timing and behavioral information without direct access to the actual circuit implementation, thus protecting IP while enabling simulation.
3Measurement precision
If actual gate delay information is revealed for accurate simulation, then simulation accuracy is improved, but IP protection deteriorates
Solution Approach 1:
The patent applies encryption transformations to the gate delay parameters, converting actual delay values into encrypted representations. These encrypted parameters maintain the mathematical relationships needed for accurate timing simulation while hiding the actual delay values that would reveal circuit implementation details.
Solution Approach 2:
The system creates encrypted copies of the delay information that preserve the timing relationships necessary for accurate simulation. These copies allow precise timing analysis without exposing the actual delay characteristics that could be used to infer the circuit implementation.
4Reliability
If encrypted circuit description is used to protect IP, then IP protection is improved, but simulation functionality deteriorates
Solution Approach 1:
The encryption scheme is designed to preserve the essential behavioral and timing parameters needed for simulation while transforming the structural identification parameters. This allows simulators to function with encrypted descriptions, maintaining simulation functionality while achieving IP protection.
Solution Approach 2:
The patent creates functional copies of the circuit description in encrypted form that retain all necessary simulation capabilities. These encrypted copies enable full simulation functionality including fault analysis and timing verification without requiring access to the actual unencrypted IP implementation.
Data Source
AI summary
A system for creating protected functional descriptions of integrated circuits provides encrypted gate delay information preventing deduction of gate function from gate delay but allowing simulation of the integrated circuit with accurate propagation delay calculation. Individual gate delay values may be modified so that they obscure actual gate delays but so that the modified individual gate delays total to equal the actual cumulative gate delay along a given data propagation path.