Encrypted GPU Buffer Paging Beyond HPA-Based AES-XTS Limits
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Solution Overview
Problem
Accelerator devices with encrypted data using AES XTS encryption cannot be paged out due to the reliance on hardware physical addresses as encryption tweaks, preventing secure paging when the CPU is outside the trusted compute base.
Innovation Solution
Implement a hardware paging engine that supports paging of encrypted memory into a special crypto domain, decoupling encryption from hardware paging addresses to maintain data security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If AES XTS encryption with hardware physical address as tweak is used, then data security is improved, but paging capability deteriorates
Solution Approach 1:
The system segments the address space into encrypted and unencrypted portions, with the upper bits of the physical address used for encryption tweaks and lower bits for paging operations. This allows simultaneous support for both secure encryption and paging functionality.
Solution Approach 2:
A page table mechanism is introduced as an intermediary layer that maps virtual addresses to physical addresses while maintaining the encryption tweak requirements. The page tables store mappings that allow the system to decrypt data at new physical addresses using appropriate tweaks derived from the page table entries.
2Reliability
If data is encrypted using hardware physical address as tweak, then encryption strength is improved, but memory address flexibility worsens
Solution Approach 1:
The system dynamically adjusts the encryption tweak based on the virtual-to-physical address mapping. When pages are moved to different physical locations, the tweak is updated accordingly through page table entries, allowing the encryption parameters to adapt dynamically to memory management operations.
Solution Approach 2:
The encryption parameters (specifically the tweak) are changed based on the virtual address rather than being fixed to the physical address. This parameter change allows the same physical address to be encrypted with different tweaks depending on which virtual address it maps to, enabling both strong encryption and address flexibility.
3Reliability
If paging is disabled for AES XTS encrypted buffers, then data security is maintained, but system productivity deteriorates
Solution Approach 1:
The system implements self-service paging for encrypted buffers by automatically managing the encryption/decryption process during page faults. When a paged-in buffer needs to be accessed, the system automatically retrieves the appropriate tweak from the page table and decrypts the data, making the security mechanism transparent to the application while enabling paging.
Data Source
AI summary
Described herein is a paging technique that can be implemented in any accelerator with attached memory and support for operating on encrypted data when the CPU is not within the trusted compute base (TCB). Memory storing data that is encrypted using hardware physical address (HPA)-based encrypted can be paged out of accelerator device memory by decoupling encryption from the hardware physical address and re-encrypting the data for page-out. Upon page-in, the data is decrypted, the integrity and authenticity of the data is verified, then the data is re-encrypted using HPA-based encryption.