Encrypted HLL Core Protection in High Level Synthesis
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Solution Overview
Problem
Existing electronic system design methods lack effective protection and usage management for high-level programming language (HLL) cores, particularly in high-level synthesis, where internal workings and usage rights are not adequately secured or propagated during circuit design and implementation.
Innovation Solution
A method and system that detect and encrypt HLL cores using session keys and public keys, generating an encrypted intermediate representation (IR) and hardware description language (HDL) circuit design, ensuring that usage rights are propagated and enforced throughout the design process, while maintaining protection by keeping the decrypted core in volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If HLL cores are provided in encrypted form for high level synthesis, then protection and usage rights enforcement are improved, but decryption and processing capabilities are worsened
Solution Approach 1:
The patent introduces a high level synthesis tool as an intermediary component that bridges the encrypted HLL core and the hardware designer. This tool decrypts the encrypted HLL core in a secure environment, processes it through the synthesis flow, and generates encrypted HDL representations. The intermediary handles the decryption and processing operations without exposing the internal workings to the hardware designer, thus maintaining protection while enabling functionality.
Solution Approach 2:
The patent segments the processing system into distinct components: the encrypted HLL core, the high level synthesis tool, and the hardware designer's environment. The HLL core remains encrypted during storage and transmission, while only the necessary processing occurs in controlled environments. This segmentation allows the core to maintain security while still being processed through the synthesis workflow.
2Reliability
If HLL cores are encrypted to protect internal workings, then security is improved, but usability and functionality are worsened
Solution Approach 1:
The high level synthesis tool serves as an intermediary that translates the encrypted HLL core into an encrypted HDL representation while maintaining security. This intermediary enables the core to be processed and integrated into larger designs without exposing its internal workings, thus preserving both security and usability.
Solution Approach 2:
The patent creates an encrypted copy of the HLL core that can be processed through the synthesis tool. This encrypted copy maintains the security properties of the original while enabling functional operations. The encrypted HDL representation generated from the encrypted HLL core can be used in hardware designs without revealing the original core's internal structure.
3Reliability
If usage rights are propagated through the synthesis process, then protection is improved, but process complexity is worsened
Solution Approach 1:
The patent merges the usage rights management functionality into the high level synthesis tool itself. The tool automatically propagates usage rights information throughout the synthesis process, from the encrypted HLL core through to the final encrypted HDL representation. This integration eliminates the need for separate, complex rights management systems while maintaining enforcement.
Solution Approach 2:
The high level synthesis tool performs self-service by automatically handling the propagation of usage rights during the synthesis process. The tool manages its own security and licensing requirements without requiring external intervention or complex manual processes, thus reducing overall system complexity while maintaining protection.
Data Source
AI summary
High level synthesis for a circuit design may include detecting, using a processor, an encrypted, high level programming language (HLL) core for inclusion in a circuit design, decrypting, using the processor, the encrypted HLL core into volatile memory, and generating, using the processor, an encrypted, intermediate representation (IR) of the circuit design including an encrypted IR of the HLL core. An encrypted hardware description language (HDL) circuit design may be generated, using the processor, from the encrypted IR of the circuit design. The encrypted HDL circuit design includes an encrypted HDL core that is functionally equivalent to the encrypted HLL core.