Encrypted Data Streaming Across Multi-Tile Processors
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Solution Overview
Problem
Multi-tile processing systems face challenges in securely transferring sensitive code and data due to difficulties in ensuring data integrity and privacy, especially when using untrusted external memories.
Innovation Solution
A multi-tile processing system with encryption units that encrypt and decrypt data using a protocol involving initialization vectors and authentication tags, allowing secure data streams between tiles and external memory, and implementing secure checkpointing and shuffling mechanisms to handle failures and optimize data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data is streamed from multiple sources to multiple destinations through a single switch, then device complexity is reduced, but the switch becomes a bottleneck that limits data transfer rates and processing capacity
Solution Approach 1:
The patent divides the monolithic switch into multiple smaller processing tiles that operate in parallel. Each tile handles a subset of data streams, allowing the system to scale processing capacity by adding more tiles without proportionally increasing overall system complexity.
Solution Approach 2:
The patent transitions from a single-dimensional switch architecture to a multi-dimensional tiled architecture. Data streams are distributed across multiple tiles along different dimensions (input ports, output ports, processing stages), enabling parallel processing and eliminating the single switch bottleneck.
2Ease of operation
If a single switch handles all data routing, then ease of operation is maintained, but the switch cannot keep up with increasing data rates from multiple sources
Solution Approach 1:
The routing function is segmented across multiple tiles, each with its own routing logic. This allows distributed decision-making that maintains operational simplicity while achieving higher aggregate processing speeds through parallel operation of multiple tiles.
Solution Approach 2:
The patent introduces intermediate buffering and routing stages between data sources and destinations. These intermediaries distribute data across multiple tiles, allowing the system to maintain simple end-to-end routing semantics while achieving high-speed parallel processing through multiple intermediate processing points.
3Productivity
If multiple switches are used to increase processing capacity, then data transfer rate improves, but device complexity and inter-switch communication overhead increase
Solution Approach 1:
The patent merges multiple switch functions into a unified multi-tile architecture. Instead of separate switches communicating through complex inter-switch fabric, multiple processing tiles are integrated into a single coordinated system that shares common control and buffering resources, reducing overall system complexity while maintaining high processing capacity.
Solution Approach 2:
Each tile in the multi-tile switch is designed to be universal and multi-functional, capable of handling any data stream routing decision. This universality eliminates the need for specialized routing logic in different switches, simplifying the overall system architecture while providing scalable processing capacity through parallel tile operation.
Data Source
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AI summary
A processing system comprising one or more chips, each comprising a plurality of tiles is described. Each tile comprises a respective processing unit and memory, the memory storing a codelet. The processing system has at least one encryption unit configured to encrypt and decrypt data transferred between the tiles and a trusted computing entity via an external computing device. The codelets are configured to instruct the tiles to transfer the encrypted data by reading from and writing to a plurality of memory regions at the external memory such that a plurality of streams of encrypted data are formed, each stream using an individual one of the memory regions at the external computing device.