Encryption Circuit Logic Gate Power Masking
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Solution Overview
Problem
Existing electronic circuits face security vulnerabilities due to side-channel analysis attacks, where attackers can infer encryption keys by analyzing power consumption and electromagnetic waves, despite the use of encryption/decryption circuits.
Innovation Solution
The electronic circuit employs logic gates configured to operate in different modes based on a control value and clock signal, maintaining a constant number of logic gates active and power consumption, making it difficult for attackers to discern the encryption/decryption operations and thus protecting against side-channel attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encryption/decryption circuit is used to protect data, then security against direct data manipulation is improved, but vulnerability to side-channel analysis attacks remains
Solution Approach 1:
The patent introduces an intermediary mechanism (the circuit configured to generate the third signal based on the first and second signals) that mediates between the encryption/decryption operations and the external environment. This intermediary creates a constant power consumption signature that masks the actual cryptographic operations from side-channel analysis while still allowing the encryption/decryption function to execute properly.
2Adaptability or versatility
If logic gates operate in different modes to perform encryption/decryption, then operational flexibility is improved, but power consumption variability increases making the circuit susceptible to side-channel attacks
Solution Approach 1:
The patent applies parameter changes by modifying the operational parameters of the logic gates through the generation of the third signal. The third signal adjusts the power consumption parameter of the logic gates to maintain a constant level regardless of whether encryption or decryption operations are performed. This parameter modification allows the circuit to maintain operational flexibility while eliminating power consumption variability that would otherwise expose it to side-channel analysis.
3Productivity
If the number of active logic gates is varied during encryption/decryption operations, then computational efficiency is improved, but detectability by attackers increases
Solution Approach 1:
The patent implements a feedback mechanism where the circuit continuously monitors and adjusts the operation of logic gates based on the generated third signal. The third signal provides feedback information that ensures the number of active logic gates remains constant while still allowing efficient encryption/decryption operations to proceed. This feedback loop prevents detectability by attackers while maintaining computational efficiency.
Data Source
AI summary
An electronic circuit includes an operator including logic gates configured to perform either one or both of encryption and decryption operations. The electronic circuit further includes a controller configured to control the operator to operate in a first mode in which each of the logic gates outputs a first logic value during a first time period of a clock signal, and operate in a second mode in which a number of first logic gates, each of which outputs the first logic value, among the logic gates, and a number of second logic gates, each of which outputs a second logic value, among the logic gates, are maintained constant during a second time period of the clock signal, in response to a control value indicating that either one or both of the encryption and decryption operations are performed.