Encryption Circuit Segmentation for Power Analysis Resistance
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Solution Overview
Problem
Existing encryption processing circuits face challenges in inhibiting leakage of secret information from bit transitions while maintaining a favorable performance/area ratio, and they are vulnerable to side channel attacks such as differential power analysis.
Innovation Solution
The proposed solution involves an encryption processing circuit that uses multiple sets of encryption blocks and registers, where each set performs encryption or decryption steps, and intermediate data is stored in subsequent registers, preventing continuous storage of data and processed data in the same register, thereby reducing correlations between bit transitions and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If WDDL (Wave Differential Dynamic Logic) is used to equalize power consumption by using complementary circuits, then resistance to differential power analysis attacks is improved, but circuit area increases and operating speed decreases
Solution Approach 1:
The encryption processing circuit is divided into multiple processing units (first processing unit, second processing unit, third processing unit) that operate in parallel. Each unit handles a portion of the encryption steps, allowing the circuit to achieve security against power analysis attacks without requiring every individual gate to be part of a complementary pair, thus reducing overall circuit area while maintaining resistance to differential power analysis.
2Reliability
If WDDL is used to equalize power consumption, then resistance to differential power analysis attacks is improved, but operating speed decreases due to precharge operations
Solution Approach 1:
The encryption process is segmented into multiple parallel processing units that can operate simultaneously. This segmentation allows the circuit to avoid sequential precharge operations while still achieving power consumption equalization through the parallel architecture, thereby maintaining higher operating speed while providing resistance to differential power analysis attacks.
Solution Approach 2:
The circuit employs periodic switching between different processing units and uses clocked operations to control the flow of data through the parallel units. This periodic action allows the system to maintain regular power consumption patterns without requiring continuous precharge operations, thus preserving operating speed while achieving security against power analysis.
3Loss of information
If multiple sets of encryption blocks and registers are used to prevent continuous storage of data in the same register, then leakage of secret information from bit transitions is inhibited, but device complexity increases
Solution Approach 1:
The encryption circuit is segmented into multiple processing units (first, second, and third processing units) that handle different steps of the encryption process. Data is distributed across these units and intermediate results are stored in different registers depending on which processing unit is active. This segmentation prevents continuous storage of sensitive data in a single register, reducing information leakage from bit transitions while managing complexity through modular design.
Solution Approach 2:
The circuit periodically switches between different processing units and uses selective data routing to move data between registers. This periodic switching ensures that sensitive data does not remain continuously in the same register, thereby preventing leakage from bit transitions. The use of control signals to manage data flow between units allows the system to achieve security without permanently duplicating all encryption blocks.
Data Source
AI summary
An encryption processing circuit capable of inhibiting leakage of secret information from bit transitions of a register while inhibiting an increase in performance/area ratio is provided.N (N is an integer equal to 2 or greater) sets, each of which including an encryption block and a register, are included, wherein an encryption block of an i-th set performs encryption in a certain step on plain text stored in the register of the i-th set or intermediate data stored in the register of the i-th set obtained from the plain text and the intermediate data obtained by the encryption is stored in the register of an (i+1)-th set and the encryption block of an N-th set performs the encryption in the certain step on plain text stored in the register of the N-th set or intermediate data stored in the register of the N-th set obtained from the plain text and the intermediate data obtained by the encryption is stored in the register of a first set.