Encryption Security via Asymmetric Clock Frequency Control
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Solution Overview
Problem
Contemporary data encryption schemes using random or pseudorandom number sequences face challenges in distributing and protecting these sequences, as attackers can access the entire set if they gain physical possession of the storage device, leading to tampering and security breaches.
Innovation Solution
The proposed solution involves an integrated circuit design that uses arbitrarily long random or pseudorandom sequences for encryption, where a clock generator and clock divider manage access frequencies to store and retrieve encryption sequences, limiting the rate at which they can be read, thereby enhancing tamper resistance and security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encryption sequences are stored in memory for distribution and use, then encryption functionality is enabled, but attackers can access the entire set if they gain physical possession of the storage device
Solution Approach 1:
The patent implements different clock frequencies for writing and reading encryption sequences from memory. The write operation uses a first clock frequency while the read operation uses a second, lower clock frequency. This dynamic frequency adjustment creates asymmetric access speeds that prevent attackers from quickly extracting the entire encryption sequence even if they gain physical access to the storage device.
Solution Approach 2:
The patent changes the temporal parameter of data access by imposing a time delay on read operations through the lower clock frequency. This parameter modification ensures that even if an attacker obtains physical access to the memory containing encryption sequences, they cannot rapidly access the entire set, thereby enhancing tamper resistance and security.
2Reliability
If arbitrary lengths of random sequences are used for encryption, then security is enhanced, but the time required to access and process the sequences increases
Solution Approach 1:
The patent segments the encryption sequence access process into two distinct phases: a fast write phase using a higher clock frequency for loading sequences into memory, and a controlled read phase using a lower clock frequency for retrieving sequences during encryption operations. This segmentation allows arbitrary-length sequences to be stored securely while managing access time through frequency control.
Solution Approach 2:
By dynamically adjusting the clock frequency based on the operation type (write vs. read), the system optimizes both security and performance. The write operation benefits from higher speed for efficient sequence loading, while the read operation uses lower frequency to prevent rapid extraction, thus balancing security requirements with operational efficiency.
3Reliability
If the read speed of encryption sequences from memory is limited, then tamper resistance increases, but encryption process speed decreases
Solution Approach 1:
The patent employs periodic clock signals with different frequencies for write and read operations. The write operation uses a higher frequency periodic signal for rapid sequence loading, while the read operation uses a lower frequency periodic signal that inherently limits the rate at which encryption sequences can be accessed, thereby maintaining tamper resistance.
Solution Approach 2:
The system changes the clock frequency parameter based on the operational phase. During write operations, a higher frequency is applied for efficient data loading. During read operations, a lower frequency is applied to control the access rate and enhance tamper resistance. This parameter change strategy balances security requirements with operational needs.
Data Source
AI summary
Systems and methods for integrated communication security are described. One aspect includes a clock generator configured to generate a clock signal at a first frequency, and a circuit utilizing the clock signal. The circuit may include a port configured to receive an encryption sequence at the first frequency, and a first unidirectional data path between the port and a memory configured to permit data transfer from the port to the memory. The memory may be configured to access the encryption sequence from the port via the first unidirectional data path and store the data. The circuit may further include a clock divider configured to divide the first frequency by a divisor deriving another clock signal at a second frequency, and an encryption/decryption module configured to read a portion of the encryption sequence from the memory, process input using the portion of the encryption sequence, and generate output responsive to the processing.