Encryption Circuit Using Dirty Bit Schemes for Reduced Initialization Time
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Solution Overview
Problem
Current encryption/decryption technologies, such as those using RC4, face challenges in reducing gate count and increasing speed while maintaining performance, especially in handheld/mobile applications where size and power consumption are critical, and existing solutions do not efficiently address the overhead in communication processes.
Innovation Solution
The implementation of an integrated circuit with execute circuitry that updates data in overlapping iterations using dual-port memory banks and a dirty bit scheme to reduce S-box initialization time, along with a look-ahead mechanism for concurrent processing of multiple bytes, optimizing memory usage and processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional encryption/decryption circuits are used, then security functionality is provided, but gate count is high and power consumption is excessive
Solution Approach 1:
The encryption/decryption circuit is divided into multiple parallel processing units, each handling a portion of the data stream. This segmentation reduces the gate count per unit while maintaining overall encryption performance through parallel operation
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by adding a temporal dimension to the operation. Multiple data elements are processed simultaneously across different time cycles, reducing the total gate count required while maintaining security performance
2Productivity
If encryption/decryption speed is increased, then throughput is improved, but initialization time becomes a bottleneck
Solution Approach 1:
The S-box initialization is performed in advance and stored in pre-configured memory structures. During operation, pre-computed values are retrieved rather than calculated in real-time, dramatically reducing initialization time while maintaining high throughput
Solution Approach 2:
The patent implements dynamic initialization where the S-box is configured once and then reused multiple times. The system transitions from a static re-initialization approach to a dynamic reuse approach, eliminating repeated initialization overhead
3Quantity of substance
If memory usage is optimized, then device size is reduced, but concurrent processing capability is limited
Solution Approach 1:
Memory is divided into multiple banks that can be accessed concurrently. Each bank handles a portion of the data, enabling parallel memory access without requiring a proportional increase in total memory size
Solution Approach 2:
Multiple memory access operations are merged into a single unified memory structure with shared read/write ports. This consolidation reduces total memory element count while maintaining concurrent access capability through intelligent port management
4Productivity
If processing efficiency is improved, then throughput increases, but power consumption rises
Solution Approach 1:
The circuit operates in periodic cycles where intensive processing is alternated with lower-power states. Data is processed in batches with idle periods between operations, reducing average power consumption while maintaining high peak throughput
Solution Approach 2:
The patent implements continuous processing pipelines where data flows through multiple stages without interruption. This eliminates idle cycles and re-initialization overhead, improving processing efficiency while reducing the total energy required per unit of data processed
Data Source
AI summary
A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line. The selector circuit (1412) responds to a state on a dirty bit line (db) to couple data bits related to the address bits themselves from the address line (1421) to the selector output (1412). Other circuits and methods of manufacture and operation are also disclosed.