Positive-Logic FET Switch Stack Without RF Terminal Capacitors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
FET-based RF switch circuits face limitations in handling high voltage RF signals without requiring negative bias voltages and large terminal capacitors, which consume IC area and increase insertion loss.
Innovation Solution
A FET-based RF switch stack that uses a stack of positive-logic FETs series-coupled with end-cap FETs, where switch circuits are employed between the RF signal source and the gate of end-cap FETs to control voltage swing, eliminating the need for terminal capacitors and allowing high voltage RF signal handling without negative bias voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If terminal capacitors are used to prevent forced ON states of end-cap FETs at high power levels, then power handling capability is improved, but IC area consumption increases and insertion loss increases
Solution Approach 1:
The patent removes terminal capacitors from the FET stack configuration. Instead of using capacitors to prevent forced ON states, the invention uses a modified biasing scheme with positive-logic FETs and end-cap FETs where the gate of the end-cap FET is connected directly to the RF signal source without a capacitor, thereby eliminating the area consumption and insertion loss associated with terminal capacitors while maintaining power handling capability.
Solution Approach 2:
The patent changes the biasing parameters of the FET stack by using positive-logic FETs that operate with positive control voltages and require a negative VGS to turn OFF. This parameter change allows the end-cap FET to be controlled differently, preventing forced ON states without requiring terminal capacitors, thus resolving the contradiction between power handling and IC area consumption.
2Reliability
If terminal capacitors are used to prevent forced ON states of end-cap FETs at high power levels, then power handling capability is improved, but insertion loss increases
Solution Approach 1:
The patent removes terminal capacitors from the FET stack configuration. Instead of using capacitors to prevent forced ON states, the invention uses a modified biasing scheme with positive-logic FETs and end-cap FETs where the gate of the end-cap FET is connected directly to the RF signal source without a capacitor, thereby eliminating the area consumption and insertion loss associated with terminal capacitors while maintaining power handling capability.
3Strength
If a stack of FETs is used to withstand high drain-source voltage, then voltage handling capability is improved, but device complexity increases
Solution Approach 1:
The patent divides the voltage handling requirement into segments by stacking multiple FETs in series, where each FET withstands a portion of the total drain-source voltage. This segmentation allows the system to handle high voltages while using standard low-voltage FET components, resolving the contradiction between voltage handling capability and device complexity by breaking down the complex high-voltage requirement into simpler manageable segments.
Solution Approach 2:
The patent uses positive-logic FETs that can serve multiple functions: they provide voltage division in the stack, enable positive logic operation without negative voltage supplies, and when configured as end-cap FETs with their gates connected to the RF signal source, they prevent forced ON states at high power levels. This multi-functionality reduces overall device complexity while maintaining voltage handling capability.
Data Source
AI summary
A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative VGS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.