Endoscope Imaging Device TSV Chip Lamination
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Solution Overview
Problem
Imaging devices for endoscopes face limitations in improving image quality due to the pixel rate being constrained by transmitting analog signals, especially with an increase in the number of pixels, necessitating the inclusion of an A/D conversion circuit to convert signals into digital form for effective transmission.
Innovation Solution
The imaging device comprises a first chip with a light receiving unit and a read circuit, and a second chip with a timing control circuit, A/D conversion circuit, and cable transmission circuit, connected via through-silicon vias (TSVs) in a laminated configuration, allowing for efficient A/D conversion and digital signal transmission, while minimizing chip area through strategic placement of connection units and circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If imaging signals are transmitted as analog signals via cable, then the transmission is simple, but the pixel rate is limited and image quality cannot be improved with increased pixel count
Solution Approach 1:
The patent transitions from analog signal transmission to digital signal transmission, representing a fundamental dimensional change in the signal domain. This allows the system to overcome the pixel rate limitations of analog transmission while maintaining compatibility with existing cable infrastructure through the cable transmission circuit.
Solution Approach 2:
The patent replaces the analog transmission mechanism with a digital transmission mechanism. By substituting analog signals with digitally converted signals processed through the A/D conversion circuit, the system achieves higher pixel rates and improved image quality while managing complexity through integrated circuit design.
2Area of stationary object
If peripheral circuit is provided in a separate chip to reduce chip area, then the chip area is reduced, but the connection between chips increases complexity
Solution Approach 1:
The patent divides the imaging device into two separate functional chips: a first chip containing the light receiving unit and read circuit, and a second chip containing the A/D conversion circuit and cable transmission circuit. This segmentation reduces the area requirements for each individual chip while maintaining all necessary functions through inter-chip connections.
Solution Approach 2:
The patent introduces connection units with through-silicon vias as intermediaries between the first chip and second chip. These connection units facilitate electrical communication between the separated chips, enabling the segmented architecture to function as an integrated system while managing the complexity of inter-chip connections.
3Area of stationary object
If chips are connected with through-silicon via to laminate separate chips, then the chip area is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent implements a laminated chip structure where the first chip and second chip are stacked in nested layers, connected through through-silicon vias. This three-dimensional nesting arrangement reduces the overall footprint and chip area while concentrating the inter-chip connections in vertical through-holes, thereby managing alignment precision requirements through the via structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-bandwidth digital signal transmission, allowing for an increase in the number of pixels and improved image quality, while maintaining a small chip area and enhancing electrical tolerance.
Implementation Method 1
the chips are connected with a through-silicon via (TSV: Si through-electrode)
Data Source
AI summary
An imaging device includes: a first chip including a light receiving unit, and a read circuit; a second chip including a timing control circuit, an A/D conversion circuit, and a cable transmission circuit; and a connection unit configured to connect the first and the second chips. The read circuit includes a column read circuit and a horizontal selection circuit, and a vertical selection circuit. The connection unit of the first chip is provided in a first area along a side of the rectangular light receiving unit, and in a second area adjacent to the column read circuit, the horizontal selection circuit, and the vertical selection circuit. The connection unit of the second chip is provided in a third area around the timing control circuit, the A/D conversion circuit, and the cable transmission circuit and in a fourth area adjacent to the timing control circuit and the A/D conversion circuit.