Endoscope Processor Phase Synchronization Control

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Solution Overview

Problem

Conventional endoscope systems face challenges in synchronizing the phase of the image pickup signal with the phase of the reference clock signal, leading to suboptimal image processing and display, especially when using high-pixel image pickup devices or varying cable lengths.

Innovation Solution

An endoscope system incorporating a processor with a PLL circuit, synchronization detection section, and control section that generates a reference clock signal and synchronizes the image pickup signal with the reference clock, detecting synchronization states to control signal processing and output either processed video or a placeholder signal when synchronization is lost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If phase synchronization between image pickup signal and reference clock signal is not ensured, then device complexity is reduced, but image processing quality deteriorates

Engineering Contradiction:
Improvesynchronization control complexityVSAvoidimage processing quality
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent implements a feedback mechanism where the synchronization detection section continuously monitors the synchronization state between the image pickup signal and reference clock signal, and the control section adjusts the signal processing based on this feedback. This ensures high image processing quality is maintained only when synchronization is achieved, while avoiding unnecessary complexity during synchronization failures.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the operational parameters of the signal processing circuit based on the synchronization state. When synchronization is detected, the circuit processes the image pickup signal; when not synchronized, it outputs a predetermined video signal. This parameter change approach resolves the contradiction by adapting system behavior to synchronization status.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If synchronization detection and control sections are added, then phase synchronization reliability is improved, but device complexity increases

Engineering Contradiction:
Improvephase synchronization reliabilityVSAvoidprocessor structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The control section serves multiple functions: it controls the signal processing circuit based on synchronization state, determines what to output (processed video or predetermined video signal), and coordinates the overall operation of the processor. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while maintaining high synchronization reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If signal processing is performed without phase synchronization, then productivity is maintained, but image quality deteriorates

Engineering Contradiction:
Improveimage processing throughputVSAvoidimage quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent maintains continuous operation by always outputting a video signal - either the processed image pickup signal when synchronized or a predetermined video signal when not synchronized. This continuity ensures the system remains productive without interruption, while image quality is maintained at high levels during synchronized operation through proper signal processing.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS8934004B2Endoscope system
Publication Date: 2015.01.13 OLYMPUS CORPORATION(JP)
  • US8934004B2 patent drawing
  • US8934004B2 patent drawing
  • US8934004B2 patent drawing

AI summary

An endoscope system includes an endoscope including a CCD for generating an image pickup signal, and a processor including a video processing circuit. The processor includes: a VCXO that generates a reference clock signal; a PLL circuit that synchronizes a phase of the image pickup signal to be inputted and a phase of the reference clock signal; a synchronization detection circuit that detects whether the phase of the image pickup signal synchronizes with the phase of the reference clock signal; and a multiplexer that controls the video processing circuit, on the basis of the detection result by the synchronization detection circuit, to cause the video processing circuit to output a predetermined video when a non-phase-synchronized state is detected, and to cause the video processing circuit to output a video signal obtained by processing the image pickup signal by the video processing circuit when a phase-synchronized state is detected.