Energy Dispersal Circuit with Packet-Based Shift Register Initialization

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Solution Overview

Problem

Conventional energy dispersal units in digital broadcast receivers require significant initialization time, leading to standby periods before correct signal output, especially during channel switching, due to frame cycle timing differences across channels.

Innovation Solution

An energy dispersal circuit that calculates and initializes the shift register value based on packet numbers and bit operations, allowing immediate commencement of the energy dispersal process without standby time, using a single energy dispersal unit for hierarchical transmissions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the energy dispersal unit initializes the shift register at frame leading position, then the energy dispersal process can be properly synchronized, but a standby time is generated from start of signal reception to frame leading position

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidstandby time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent pre-calculates and stores the initial values of the shift register for multiple channels in advance. When channel switching occurs, the stored initial value corresponding to the target channel is immediately loaded into the shift register, eliminating the need to wait for the next frame leading position. This preliminary preparation of initial values resolves the contradiction by enabling immediate energy dispersal initialization while maintaining proper synchronization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent makes the initial value of the shift register dynamic and adaptable to different channels. Instead of using a fixed initial value or waiting for frame synchronization, the system dynamically selects and applies channel-specific initial values based on the current channel being received. This dynamic approach allows the energy dispersal unit to be properly synchronized for each channel without incurring standby time.

Inventive Principle:
Principle #15Dynamics

2Reliability

If multiple energy dispersal units are provided for hierarchical transmissions, then channel switching can be handled properly, but the circuit configuration becomes complex

Engineering Contradiction:
Improvechannel switching accuracyVSAvoidcircuit configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes a single energy dispersal unit universal by enabling it to handle multiple channels through dynamic initial value loading. The same shift register and XOR circuitry are used across all channels, with the initial value being the variable parameter that adapts to different channels. This multi-functionality approach achieves proper channel switching handling without requiring separate energy dispersal units for each channel, thereby avoiding increased circuit complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the parameter of the shift register initial value to accommodate different channels. Instead of duplicating the entire energy dispersal unit for each channel, the system modifies only the initial value parameter based on the target channel. This parameter-based differentiation allows a single energy dispersal unit to properly handle hierarchical transmissions across multiple channels while maintaining a simple circuit configuration.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7505536B2Energy dispersal circuit and receiver
Publication Date: 2009.03.17 REDWOOD TECHNOLOGIES LLC
  • US7505536B2 patent drawing
  • US7505536B2 patent drawing
  • US7505536B2 patent drawing

AI summary

An energy dispersal circuit, which generates a PRBS (Pseudo Random Binary Sequence) and executes an XOR (exclusive-OR) operation with respect to a data signal and the PRBS based on a bit, includes a register value calculator for calculating a register value of a shift register based on inputted data and a packet number. The register value calculator has a bit divider for dividing the packet number from LSB to MSB, packet shift operators for bit-shifting an initial value of the shift register from 20 bits to 2N−1 bits, and selectors for selecting inputs and outputs thereof.