Engine Power Gating Arbitration to Limit Switching Current Surges

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Solution Overview

Problem

Conventional sleep and standby mode techniques in integrated circuits cause large switching current surges, leading to noise, logic errors, and potential damage due to increased power consumption and leakage current, necessitating improved power management methods.

Innovation Solution

The implementation of engine level power gating arbitration techniques, where a power gating arbiter prioritizes and sequences requests from engine level power gating controllers to switch engines on or off, minimizing switching current surges by controlling power switching in a predetermined order.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If circuits are selectively turned off to conserve power, then power consumption is reduced, but switching current surges cause noise, logic errors, and potential damage

Engineering Contradiction:

Improvepower consumptionVSAvoidswitching current induced noise and circuit damage

Core Design Contradiction:

Loss of energyVSObject-affected harmful factors

Solution Approach 1:

The power gating arbiter performs preliminary sequencing of power gating requests before executing the actual power switching. By prioritizing and ordering the requests in advance, the system controls the timing and sequence of power transitions, preventing simultaneous switching that causes current surges while ensuring power is reduced when circuits are idle

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The power gating arbiter acts as an intermediary between multiple power gating controllers and the power distribution network. It receives requests from multiple controllers, sequences them according to priority, and manages the power switching process to prevent harmful current surges while achieving power conservation goals

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8762761B2Engine level power gating arbitration techniques

Publication Date: 2014.06.24 NVIDIA CORP

AI summary

An integrated circuit, in accordance with embodiments of the present technology, includes a plurality of engines, a plurality of engine level power gating (ELPG) controllers, and a power gating arbiter for implementing engine level power gating arbitration techniques. The power gating arbiter may receive requests from one or more ELPG controllers to turn on their respective engines or portions therein. The power gating arbiter prioritizes the request and sends an acknowledgment to a given ELPG controller to turn on or off its corresponding engine according to the prioritized predetermined order. After receiving the acknowledgement, the given ELPG controller turns on or off its corresponding engine and returns an indication to the power gating arbiter that the corresponding engine is turned on or off. The process may be iteratively repeated for each received request after receiving the indication from the previously serviced ELPG controller that its corresponding engine is turned on or off.