Engineered Epi Stacks for Precise Wafer Thinning Control

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Solution Overview

Problem

Current semiconductor manufacturing techniques struggle to achieve precise control over the total thickness remaining and total thickness variation of substrates during the thinning process, which is critical for advanced memory and logic devices.

Innovation Solution

The method involves forming a semiconductor device structure with engineered epitaxial layers that include selectively removable layers, allowing for precise control through etching processes, and bonding a component substrate assembly to the device structure using a bonding layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If wafer grinding and CMP solutions are used for substrate thinning, then substrate thickness can be reduced, but precise control of total thickness remaining and total thickness variation cannot be achieved

Engineering Contradiction:
Improvetotal thickness remaining and total thickness variation controlVSAvoidsubstrate thinning process complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The substrate thinning process is segmented into multiple distinct steps: initial grinding to reduce thickness, followed by selective etching of engineered epitaxial layers. Each step removes a controlled portion of material, with the epitaxial layers acting as sacrificial stop layers that define the final thickness. This segmentation enables precise thickness control while simplifying the overall manufacturing process by replacing complex CMP control with simpler, more controllable etching steps.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Engineered epitaxial layers are formed on the substrate surface before the thinning process begins. These pre-formed layers serve as sacrificial stop layers that will be selectively removed during etching. By preparing these layers in advance, the final substrate thickness is predetermined by the etching depth to the stop layer, enabling precise thickness control without requiring complex real-time monitoring during the thinning process.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If SOI wafers are used to enable backside access and precise thickness control, then device structure quality can be improved, but manufacturing cost increases significantly

Engineering Contradiction:
Improvethickness control and device structure qualityVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

Engineered epitaxial layers are formed on conventional, low-cost silicon wafers to serve as sacrificial stop layers. These epitaxial layers are intentionally designed to be removed during the thinning process, similar to disposable elements. By using cheap conventional wafers with temporary epitaxial layers instead of expensive permanent SOI wafers, the same thickness control and device quality are achieved at a fraction of the cost.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The invention changes the material composition parameters of the substrate by forming engineered epitaxial layers with different crystal orientations, doping levels, or material compositions than the base substrate. These parameter changes create selective etchability, allowing the epitaxial layers to be removed while preserving the final substrate. This enables precise thickness control on conventional wafers, replacing the need for expensive SOI wafers.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of thinned device structures with precise thickness control, reducing costs and allowing for the creation of high-quality epitaxial Si layers, which is essential for advanced semiconductor devices.

Implementation Method 1

an etching process that includes the use of an etchant chemistry that selectively removes the portions of the base substrate relative to the material of the first layer

Methodology Applied
Scientific EffectSelective etching:

Implementation Method 2

an etching process that includes the use of an etchant chemistry that selectively removes the first layer relative to the material of the second layer

Methodology Applied
Scientific EffectSelective etching:

Implementation Method 3

bonding a component substrate bonding layer formed on the component substrate assembly to the bonding layer formed over semiconductor device structure assembly

Methodology Applied
Scientific EffectBonding:

Data Source

PatentUS20250132163A1Engineering epi stacks for extreme wafer thinning
Publication Date: 2025.04.24 APPLIED MATERIALS INC
  • US20250132163A1 patent drawing
  • US20250132163A1 patent drawing
  • US20250132163A1 patent drawing

AI summary

Embodiments of the present disclosure include a thinned device structure and method of forming a thinned device structure. Embodiments of the disclosure provided herein include the use of engineered epitaxial (Epi) layers that are formed on a base substrate. The engineered epitaxial layers include two or more epitaxial layers that each include materials that allow at least one of the two or more epitaxial layers to be selectively removed from the other layer(s). In some embodiments, one of the two or more formed epitaxial layers has etch selectivity (e.g., wet and/or dry etch selectivity) to materials disposed on either side of the formed layer.