Engineered Substrate for GaN and Silicon Integration
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Solution Overview
Problem
Heteroepitaxial growth of gallium nitride based compound semiconductors on sapphire, silicon carbide, and silicon substrates often results in reduced uniformity and adverse effects on electronic/optical properties due to the mismatch in material properties, necessitating improved epitaxial growth processes and substrate structures.
Innovation Solution
The use of a ceramic substrate with a polycrystalline core, encapsulating layers, and a bonding layer to facilitate the growth of gallium nitride (GaN) and silicon based devices, allowing for epitaxial growth and integration of III-V compound semiconductor devices with standard silicon processes, enabling thermal matching and low defect density layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If heteroepitaxial growth is used to grow GaN on sapphire, silicon carbide, or silicon substrates, then the growth process can be implemented, but the uniformity and electronic/optical properties of the epitaxial layers are reduced
Solution Approach 1:
The patent introduces an intermediary engineered substrate system consisting of a polycrystalline ceramic core with encapsulating layers and a bonding layer. This intermediary structure mediates between the GaN epitaxial growth and the final device application, providing a controlled interface that enables high-quality growth while managing thermal and mechanical property mismatches.
Solution Approach 2:
The patent employs composite material structures including encapsulating layers (such as silicon nitride or silicon oxide) and bonding layers (such as silicon dioxide or silicon nitride) on a polycrystalline ceramic core. These composite structures provide tailored thermal, mechanical, and chemical properties that support high-quality GaN epitaxial growth and subsequent device fabrication.
2Reliability
If a polycrystalline ceramic substrate is used with encapsulating and bonding layers, then thermal matching and low defect density can be achieved, but the substrate structure and processing become more complex
Solution Approach 1:
The patent applies preliminary actions by pre-forming the encapsulating layers and bonding layers on the polycrystalline ceramic substrate before GaN epitaxial growth. The encapsulating layers are formed to prevent contamination and outgassing during high-temperature processing, while bonding layers are prepared for subsequent wafer bonding. This preliminary preparation ensures a clean, controlled interface for epitaxial growth and simplifies subsequent processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the growth of GaN and silicon based devices with improved thermal performance and reduced defect density, allowing for the integration of CMOS, RF, LEDs, and power devices at a chip level, while maintaining uniformity and retention of thermal performance.
Implementation Method 1
a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer
Implementation Method 2
forming a gallium nitride (GaN) layer coupled to the second silicon layer by epitaxial growth
Data Source
AI summary
A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, forming a GaN layer coupled to the second silicon layer, forming a GaN based device coupled to the GaN layer, removing the engineered substrate to expose a back surface of the first silicon layer, forming a silicon based device coupled to the back surface of the first silicon layer, forming a via from the back surface of the first silicon layer, filling the via with a conducting material, and interconnecting the GaN based device and the silicon based device through the via.