Enhanced Codeword for Memory Redundancy and Diagnostics
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Solution Overview
Problem
Current computing systems face challenges in efficiently monitoring and preserving memory operation information, which is crucial for tracking memory health and performing predictive diagnostics, due to the need for additional channels and increased back-up circuitry to prevent data loss during asynchronous power loss events.
Innovation Solution
Integrating memory operation information into the codeword stored on each memory die using a die-level redundant array of independent 3D XPoint™ memory (RAIX) scheme, where the information is backed up with every write event or scrub operation, reducing the reliance on external redundancy schemes and protective capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory operation information is stored using additional channels and back-up circuitry, then data loss prevention is improved, but device complexity increases
Solution Approach 1:
The patent combines memory operation information with payload data into a single codeword structure. The codeword includes both the operation information (such as access counts, timestamps, scrub operation records) and the payload data, eliminating the need for separate storage channels and reducing circuitry complexity while maintaining data integrity and loss prevention capabilities.
2Measurement precision
If memory operation information is tracked for predictive diagnostics, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The codeword structure serves multiple functions simultaneously: it stores payload data, tracks memory operation information (access counts, timestamps, scrub operations), and enables predictive diagnostics. This multi-functional approach allows comprehensive memory health monitoring without requiring separate dedicated monitoring circuitry, thus improving measurement precision while avoiding increased device complexity.
Data Source
AI summary
Methods, apparatuses, and systems for error recovery in memory devices are described. A die-level redundancy scheme may be employed in which parity data associated with particular die may be stored. An example apparatus may include a printed circuit board and memory devices. Each memory device may be each disposed on a planar surface of the printed circuit board and may each include two or more memory die. The apparatus may also include multiple channels communicatively coupled to the two or more memory die and a memory controller. The memory controller may be communicatively coupled to the multiple channels and may deterministically maintain a redundancy scheme via data transmission through the multiple channels. The memory controller may also update memory operation information appended to the enhanced codeword in response to a memory operation request.