Enhanced GaN Transistor Using InAlN Heterostructure and P-N Junction
Solution Overview
Problem
Conventional GaN transistors with AlGaN/GaN heterostructures face limitations due to lattice mismatch, thermal expansion variance, and tensile strength issues, constraining maximum output current and requiring operation in depletion mode, leading to higher power consumption.
Innovation Solution
The use of InxAl1-xN/AlN heterostructure with a P-N junction formed by doping p-InxAl1-xN, allowing the GaN transistor to operate in enhancement mode with increased output current, achieved through epitaxy growth and surface passivation to reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If AlGaN/GaN heterostructure is used in conventional GaN transistor, then the transistor can be manufactured with existing processes, but the maximum output current is constrained due to lattice mismatch, thermal expansion variance and tensile strength issues
Solution Approach 1:
The patent changes the material composition parameters by introducing InxAl1-xN alloy layers with specific indium content (x) to improve lattice matching between the buffer layer and GaN layer, thereby reducing dislocation density and enhancing the structural reliability while maintaining high output current capability
Solution Approach 2:
The patent employs a composite heterostructure consisting of multiple layers including InxAl1-xN buffer layer, AlN barrier layer, and GaN channel layer, where each material component is selected to address specific issues: InxAl1-xN for lattice matching, AlN for high breakdown voltage and polarization, and GaN for high electron mobility, collectively achieving both high reliability and high output current
2Device complexity
If conventional GaN transistor operates under depletion mode, then the transistor structure is simpler, but the transistor consumes extra power due to negative threshold voltage causing continuous current conduction
Solution Approach 1:
The patent changes the electrical parameters of the transistor by introducing a P-type doping layer (p-InxAl1-xN) to form a P-N junction, which creates a positive threshold voltage through the built-in potential of the junction, enabling the transistor to operate in enhancement mode and eliminate continuous current conduction, thereby reducing power consumption while maintaining structural simplicity
Solution Approach 2:
The patent introduces a P-type doping layer as an intermediary element between the gate and the channel, which forms a P-N junction that acts as a mediator to control the channel conductivity. This intermediary layer enables the transistor to turn off completely by creating a depletion region that blocks current flow, solving the power consumption issue without significantly increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher output current and transconductance, suitable for high-performance and high-voltage driver circuits, improving the GaN transistor's performance and efficiency.
Implementation Method 1
the gallium nitride/aluminum nitride in its structure possesses a great amount of polar charge to form two dimension electron gas (2DEG)
Implementation Method 2
The P-N junction is formed on the top layer by doping the p-InxAl1-xN, in order to make the enhanced GaN transistor device with higher output current
Implementation Method 3
a surface passivation layer covered the drain ohmic contact, source ohmic contact, and p-element epitaxy growth layer, and covered portion of the gate structure
Data Source
AI summary
An enhanced GaN transistor is provided. The structure comprises a substrate, a heterostructure, a p-element epitaxy growth layer, a drain ohmic contact and a source ohmic contact disposed on the heterostructure and on two sides of the p-element epitaxy growth layer, a gate structure disposed on the p-element epitaxy growth layer, and is separated from the drain ohmic contact and the source ohmic contact, a surface passivation layer covered the drain ohmic contact, source ohmic contact, and p-element epitaxy growth layer, and covered portion of the gate structure.