Enhanced PCIe Endpoint Device for Multi-Socket Latency Reduction
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Solution Overview
Problem
Existing PCIe endpoint solutions face latency and jitter issues due to the need for PCIe traffic to be relayed through a single host processor, leading to increased complexity and performance variability in multi-socket host systems.
Innovation Solution
The implementation of enhanced PCIe endpoint devices that present multiple endpoints to host processors through separate PCIe controllers, allowing direct connection and reducing latency by merging traffic and processing it closer to the source, without requiring compliance with the PCIe Multi-Root I/O Virtualization (MR-IOV) specification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If PCIe traffic is relayed through a single host processor, then device complexity is reduced, but latency and jitter increase
Solution Approach 1:
The patent divides the single PCIe endpoint into multiple endpoints (first PCIe endpoint and second PCIe endpoint), each directly connected to different host processors. This segmentation allows PCIe traffic to be processed locally at each endpoint rather than being relayed through a single processor, reducing latency and jitter while maintaining manageable device complexity through modular architecture.
2Ease of operation
If PCIe traffic is relayed through a single host processor, then ease of operation is improved, but performance variability increases
Solution Approach 1:
The patent implements local quality by enabling each PCIe endpoint to independently process traffic locally at its connected host processor rather than relaying through a single processor. The first PCIe endpoint processes traffic locally at the first host processor, and the second PCIe endpoint processes traffic locally at the second host processor, ensuring consistent and reliable performance by eliminating relay-induced variability.
3Loss of time
If multiple PCIe endpoints are implemented, then latency is reduced, but device complexity increases
Solution Approach 1:
The patent applies universality by designing multiple PCIe endpoints that share common functionality and interface standards. Each endpoint (first PCIe endpoint and second PCIe endpoint) implements the same PCIe protocol and emulation capabilities, allowing them to be managed uniformly by the host system while providing low-latency local processing. This multi-functionality approach reduces latency without proportionally increasing complexity.
4Adaptability or versatility
If software emulation of peripheral devices is implemented, then adaptability is improved, but processing capacity is consumed
Solution Approach 1:
The patent introduces an intermediary approach by implementing PCIe endpoints that provide hardware-assisted emulation capabilities. Rather than relying solely on software emulation that consumes processor capacity, the PCIe endpoints act as intermediaries that handle device emulation in hardware, freeing processor resources while maintaining adaptability to support multiple virtual machines and peripheral devices through SR-IOV virtualization.
Data Source
AI summary
A system that provides virtualized computing resources to clients or subscribers may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware devices in software. In response to receiving a transaction layer packet that includes a transaction directed to an emulated device, the endpoint device may process the transaction, which may include emulating the target emulated device. The endpoint device may include multiple PCIe controllers and may expose multiple PCIe endpoints to a host computing system. For example, each PCIe controller may be physically coupled to one of multiple host processor sockets or host server SOCs on the host computing system, each of which exposes its own root complex. Traffic received by the PCIe controllers may be merged on the endpoint device for subsequent processing. Traffic originating at one host processor socket may be steered to the PCIe controller to which it is directly attached.