Enhanced P-Well Region for High Voltage Breakdown in CMOS
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Solution Overview
Problem
Conventional semiconductor devices face limitations in breakdown voltage, leading to reduced transistor lifetime due to uncontrollable current increase, and existing techniques to increase breakdown voltage often incur additional fabrication costs and process steps.
Innovation Solution
A metal oxide semiconductor field effect transistor (MOSFET) device with an enhanced p-well region is fabricated using a CMOS logic foundry technology, incorporating multiple doping profiles and offset regions to increase the breakdown voltage without increasing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional techniques (separate high voltage process, double diffused drain, cascading transistors) are used to increase breakdown voltage, then breakdown voltage is improved, but fabrication cost and process complexity increase
Solution Approach 1:
The patent merges the high voltage device fabrication into the existing CMOS logic process by forming an enhanced p-well region that integrates both low voltage transistor and high voltage LDMOS transistor fabrication. This eliminates the need for separate high voltage process steps while achieving the required breakdown voltage improvement.
Solution Approach 2:
The patent applies local quality by creating an enhanced p-well region with specific doping characteristics (higher doping concentration and/or extended depth) in targeted areas where high voltage devices are formed, while maintaining standard CMOS process conditions for other regions. This localized enhancement achieves breakdown voltage improvement without modifying the entire fabrication process.
2Adaptability or versatility
If operating voltage is increased above breakdown voltage to maintain auxiliary device performance, then device functionality is maintained, but transistor lifetime decreases due to uncontrollable current increase
Solution Approach 1:
The patent applies preliminary anti-action by pre-forming an enhanced p-well region with increased doping concentration and extended depth before device operation. This structural enhancement preemptively prevents punch-through and avalanche breakdown at higher voltages, thereby preventing uncontrollable current increase and extending transistor lifetime throughout the device's operational life.
Data Source
AI summary
An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.