Enhanced Standard Cells for Deep Submicron Yield
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Solution Overview
Problem
Deep submicron integrated circuit fabrication processes face challenges in achieving high yield and area efficiency due to unpredictable interactions and design rule restrictions, particularly in standard cell libraries, which are difficult to adapt to new processes without compromising manufacturing yields.
Innovation Solution
A method that combines standard cells from an original set of design rules with regularity restrictions and enhanced standard cells, where the enhanced cells are variants with adapted design rules to improve power, performance, and area efficiency, by stretching certain cell attributes like transistor gate widths and conductor lines, while maintaining critical cell attributes unchanged.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional standard cell libraries are scaled to meet new deep submicron design rules, then device feature sizes are reduced, but manufacturing yield becomes unacceptable due to unpredictable lithography interactions
Solution Approach 1:
The patent modifies physical and geometric parameters of standard cells including transistor gate widths, conductor line dimensions, and spacing distances to create enhanced standard cells that meet new design rules while avoiding unpredictable lithography interactions. This involves systematically adjusting cell parameters based on empirical data from deep submicron fabrication processes.
Solution Approach 2:
The patent divides the standard cell library into two segments: original standard cells that maintain traditional designs and enhanced standard cells that incorporate modified parameters. This segmentation allows designers to selectively use enhanced cells in regions where yield improvement is critical while maintaining compatibility with existing design infrastructure.
2Reliability
If additional regularity restrictions are imposed on IC layouts to address unpredictable interactions, then manufacturing yield improves, but area efficiency deteriorates
Solution Approach 1:
The patent applies regularity restrictions and enhanced cell parameters locally to specific standard cells and layout regions where unpredictable interactions occur, rather than imposing global restrictions on the entire IC layout. This localized approach maintains area efficiency in regions where restrictions are not needed while improving yield in critical regions.
3Adaptability or versatility
If existing standard cell libraries are adapted to new deep submicron processes, then compatibility with existing infrastructure is maintained, but area efficiency and performance deteriorate
Solution Approach 1:
The patent creates enhanced standard cells that copy the functional behavior and interface characteristics of original standard cells while incorporating modified physical parameters. This copying approach ensures compatibility with existing design tools, verification methodologies, and infrastructure while achieving improved area efficiency and performance in deep submicron processes.
Data Source
AI summary
The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.