Enlarged Backside Contact Structure for Low-Resistance GAA FETs
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Solution Overview
Problem
Existing methods for forming contacts in semiconductor devices, particularly in gate-all-around FETs, face challenges in reducing resistance and maintaining effective gate control as device sizes decrease, leading to increased complexity and fabrication costs.
Innovation Solution
The method involves forming an enlarged backside contact by extending the recess for the source or drain structure deeper into the substrate, using a dummy contact structure, and then replacing it with a conductive material after forming a sidewall spacer and dielectric layer, resulting in a larger backside contact that reduces resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but device performance degradation and fabrication complexity increase
Solution Approach 1:
The contact structure transitions from a planar two-dimensional configuration to a three-dimensional enlarged contact with a wider upper portion and narrower lower portion. This dimensional change allows the contact to maintain larger effective area for lower resistance while accommodating the reduced device footprint, thus improving productivity without sacrificing device performance.
Solution Approach 2:
The contact structure employs non-uniform cross-sectional geometry with different widths at different heights. The upper portion has a larger width to reduce contact resistance, while the lower portion has a smaller width to maintain gate control. This local differentiation of geometric properties resolves the contradiction between lowering resistance and maintaining gate control in scaled devices.
2Reliability
If contact size is increased to reduce resistance, then device performance is improved, but gate control and pitch density are compromised
Solution Approach 1:
The contact structure employs non-uniform cross-sectional geometry with different widths at different heights. The upper portion has a larger width to reduce contact resistance, while the lower portion has a smaller width to maintain gate control. This local differentiation of geometric properties resolves the contradiction between lowering resistance and maintaining gate control in scaled devices.
Solution Approach 2:
The contact structure transitions from a planar two-dimensional configuration to a three-dimensional enlarged contact with a wider upper portion and narrower lower portion. This dimensional change allows the contact to maintain larger effective area for lower resistance while accommodating the reduced device footprint, thus improving productivity without sacrificing device performance.
3Ease of manufacture
If conventional contact formation is used, then fabrication process is simpler, but resistance is higher and performance is degraded
Solution Approach 1:
A dummy contact structure is formed in advance during the fabrication process. This dummy structure serves as a template that guides subsequent processing steps, including the formation of the enlarged contact. The preliminary action of creating this placeholder structure enables the complex enlarged contact geometry to be achieved through systematic processing rather than requiring entirely new fabrication techniques.
Solution Approach 2:
The dummy contact structure acts as an intermediary element that facilitates the formation of the final enlarged contact. It provides a structural framework that guides material deposition and removal processes, enabling the transformation from a simple contact to an enlarged contact with optimized geometry for reduced resistance while maintaining gate control.
Data Source
AI summary
A semiconductor structure includes a stack of channel layers, a source/drain feature connected to the stack of channel layers, a gate structure wrapping around the stack of channel layers, a dielectric liner disposed on a bottom surface of the gate structure, and a source/drain contact underlying the source/drain feature and the stack of channel layers and landing on the dielectric liner. The source/drain contact is electrically connected to the source/drain feature.