Enlarged End Via Structure for Semiconductor Contact Reliability
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes, as feature sizes decrease, making fabrication processes more difficult and complex.
Innovation Solution
A semiconductor device structure is formed using a conductive via structure with an enlarged end portion, which increases the probability of connection and reduces contact resistance, achieved through a process involving multiple dielectric layers and conductive layers, with specific etching and deposition processes to create a conductive via structure that passes through different dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process difficulty increases and reliability decreases
Solution Approach 1:
The via structure transitions from a uniform cylindrical shape to a non-uniform shape with an enlarged end portion at the first dielectric layer interface. This local enlargement creates a larger connection area specifically where contact with conductive lines is needed, while maintaining smaller via dimensions in other regions to support continued scaling. The localized quality change resolves the contradiction by improving reliability at the contact interface without preventing overall feature size reduction for productivity gains.
Solution Approach 2:
The via structure evolves from a two-dimensional cross-sectional view (circular opening) to a three-dimensional shape with varying cross-sections along its depth. The enlarged end portion adds dimensional complexity to the via geometry, creating a mushroom-like or tapered structure that provides enhanced contact area in the horizontal dimension while maintaining controlled depth in the vertical dimension. This dimensional approach allows reliability improvement without sacrificing the ability to scale features.
2Area of stationary object
If feature sizes decrease to increase functional density, then more devices fit per chip area, but fabrication process complexity increases
Solution Approach 1:
The via formation process is segmented into distinct stages: forming the initial via hole through the second dielectric layer, depositing conductive material, and then selectively enlarging the end portion at the first dielectric layer interface. This segmentation allows each step to be optimized independently - the initial via can be formed with standard small dimensions for high density, while the enlargement step adds the complexity-only-where-needed feature for reliability without requiring complete process redesign.
Solution Approach 2:
The via hole is preliminarily formed with standard dimensions through photolithography and etching processes before the selective enlargement step. This preliminary action establishes the basic high-density via structure, and subsequent processing (such as selective etching or deposition) adds the enlarged end portion. This approach allows the majority of via structures to maintain simple formation processes while only requiring additional complexity at specific locations where enhanced contact is needed.
3Ease of manufacture
If standard via structures are used at smaller scales, then fabrication remains simpler, but connection reliability and yield decrease due to smaller connection area
Solution Approach 1:
The via structure implements local quality by maintaining simple cylindrical geometry for the majority of the via depth while introducing an enlarged end portion specifically at the interface with the first dielectric layer. This localized enlargement occurs only where conductive lines are present, providing enhanced connection area and reliability precisely where needed, while the rest of the via structure retains the simplicity of standard formation processes. The selective nature of the enlargement minimizes additional fabrication complexity.
Solution Approach 2:
The enlarged end portion can be formed by copying or replicating the conductive line pattern at the via interface. Photolithography masks are used to define the enlargement regions based on the underlying conductive line locations, ensuring that via enlargements are created only where needed for connection. This copying approach maintains fabrication simplicity by using established patterning processes rather than requiring entirely new manufacturing techniques.
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure includes a second dielectric layer over the first dielectric layer. The first dielectric layer and the second dielectric layer are made of different materials. The semiconductor device structure includes a conductive via structure passing through the first dielectric layer and penetrating into the second dielectric layer. The conductive via structure has a first portion and a second portion. The first portion and the second portion are in the first dielectric layer and the second dielectric layer respectively. The first portion has a first end portion facing the substrate. A first width of the first end portion is greater than a second width of the second portion.