Enlarged Via Layout Patterns Reduce Mask Count in IC Fabrication
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Solution Overview
Problem
Existing integrated circuit fabrication processes that aim to increase spatial resolution of features often require additional masks and complex exposure and etching processes, leading to increased complexity and resource consumption.
Innovation Solution
Modifying the layout design by replacing certain via layout patterns with enlarged via layout patterns, which reduces electrical resistance and simplifies the fabrication process from 7-patterning-7-etching (7P7E) to 5-patterning-5-etching (5P5E), while maintaining or improving operational frequency by about 4-5%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used to increase spatial resolution, then feature resolution is improved, but process complexity and resource consumption increase
Solution Approach 1:
The patent applies preliminary action by modifying the layout design before fabrication to incorporate enlarged via patterns. This pre-modification allows the use of simpler, fewer fabrication steps (reducing from 7P7E to 5P5E) while still achieving the required electrical performance, thereby resolving the contradiction between precision and complexity.
2Manufacturing precision
If conventional fabrication processes are used to increase spatial resolution, then feature resolution is improved, but resource consumption increases
Solution Approach 1:
By pre-modifying the layout design with enlarged via patterns, the patent reduces the number of masks and fabrication steps required. This preliminary design adjustment directly decreases resource consumption (fewer masks) while maintaining manufacturing precision through the optimized via dimensions.
3Reliability
If via layout patterns are enlarged, then electrical resistance is reduced, but via area increases
Solution Approach 1:
The patent applies parameter changes by systematically enlarging via layout patterns from conventional dimensions to optimized dimensions. This parameter modification directly reduces electrical resistance (improving reliability) while accepting the trade-off of increased via area, which is resolved through the overall layout optimization that reduces total via count and simplifies processing.
Data Source
AI summary
A method of forming a set of masks for manufacturing an integrated circuit includes determining a presence of a first via layout pattern and a power rail layout pattern in an original layout design. The first via layout pattern and the power rail layout pattern overlap each other. The first via layout pattern is part of a first cell layout of the original layout design. The power rail layout pattern is shared by the first cell layout and a second cell layout of the original layout design. The method further includes modifying the original layout design to become a modified layout design and forming the set of masks based on the modified layout design. The modifying the original layout design includes, if the first via layout pattern and the power rail are present in the original layout design, replacing the first via layout pattern with an enlarged via layout pattern.