High Speed Communications System Using ENRZ and Duobinary Encoding
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Solution Overview
Problem
High-speed digital interconnection systems face limitations in reliable, error-free data transfer due to data skew, inter-symbol interference, and increased complexity, especially at high data rates exceeding conventional communication signaling methods.
Innovation Solution
The use of a combination of ENRZ signaling, duobinary encoding, and a two-frequency channel approach, along with Hadamard transforms and ISI-controlling encodings, to achieve robust data transfer across multiple wires, optimizing signal integrity and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel data transfer with wide bus widths is used to increase throughput, then data transfer throughput is improved, but data skew and inter-symbol interference increase
Solution Approach 1:
The patent segments the data transfer process by dividing wide parallel data buses into multiple narrower buses operating at higher clock speeds. This segmentation reduces data skew and inter-symbol interference while maintaining high throughput through parallel operation of multiple segmented buses with advanced error detection and correction mechanisms.
Solution Approach 2:
The patent changes key operating parameters by transitioning from wide低速 buses to narrow high-speed buses, and by implementing dynamic clock skew compensation and adaptive equalization techniques. These parameter changes optimize signal integrity while maintaining data transfer throughput.
2Reliability
If active equalization and ISI elimination techniques are implemented, then signal integrity is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent applies preliminary action by implementing pre-emphasis filtering at the transmitter before signal transmission. This pre-compensation technique anticipates and counteracts expected signal degradation and inter-symbol interference, reducing the need for complex equalization at the receiver while improving signal integrity.
Solution Approach 2:
The patent implements feedback mechanisms through continuous time linear equalization (CTLE) and decision feedback equalization (DFE) that dynamically adjust equalization parameters based on received signal quality. This feedback loop optimizes signal integrity while adapting to changing channel conditions, reducing the need for overly complex fixed equalization designs.
3Reliability
If higher clock speeds are used in narrower buses, then data skew is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs parameter changes by implementing dynamic clock skew compensation and adaptive timing adjustment mechanisms that compensate for manufacturing variations in transmission lines. These dynamic adjustments allow the system to operate at higher clock speeds while tolerating greater manufacturing tolerances in PCB trace lengths and connector alignments.
Data Source
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AI summary
Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.