Entropy-Based Ant Colony Optimization for High Level Synthesis Throughput
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Solution Overview
Problem
High Level Synthesis (HLS) for digital circuit design faces challenges in achieving optimal throughput due to limitations in existing optimization methods, particularly in frame-based algorithms, where the synthesis process results in low throughput and inefficiencies in memory mapping and control logic for pipelined architectures.
Innovation Solution
The integration of entropy-based Ant Colony Optimization (ACO) into the HLS process for circuit design, which uses a data flow graph to simulate hardware component combinations and select the lowest-cost solution by incorporating supplemental sub-integer costs, enhancing the selection of candidate solutions and improving the design efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional High Level Synthesis (HLS) is used for digital circuit design, then the design process can be automated, but the throughput is low and the synthesis efficiency is poor
Solution Approach 1:
The patent implements dynamic scheduling in the HLS tool, allowing the synthesis process to adaptively adjust operation scheduling decisions based on real-time analysis of hardware resource availability and data dependencies. This dynamic approach enables better utilization of hardware resources and improves throughput compared to static scheduling methods
Solution Approach 2:
The patent replaces traditional mechanical optimization methods with entropy-based cost calculation. By using entropy to quantify the uncertainty and information content in scheduling decisions, the system can more efficiently evaluate and select optimal scheduling strategies, reducing synthesis time while improving throughput
2Ease of operation
If frame-based algorithms are used in HLS, then the processing of input/output data frames can be simplified, but the throughput remains low due to inefficiencies in memory mapping and control logic
Solution Approach 1:
The patent performs preliminary entropy-based cost calculation and scheduling decision-making during the synthesis phase, before the actual hardware is generated. This allows the system to pre-determine optimal memory mapping and control logic configurations for frame-based algorithms, eliminating the need for runtime optimizations and improving throughput
Solution Approach 2:
The patent changes the cost calculation parameter from traditional metric-based evaluation to entropy-based evaluation. This parameter change fundamentally alters how scheduling decisions are made, enabling the system to identify more efficient memory mapping and control logic configurations that improve frame processing throughput
3Adaptability or versatility
If Ant Colony Optimization (ACO) is applied to HLS, then multiple candidate solutions can be explored, but the selection process lacks precision due to absence of entropy-based cost calculation
Solution Approach 1:
The patent implements feedback mechanisms where entropy-based cost calculations are continuously performed on candidate solutions generated by ACO. The entropy values provide precise feedback about the quality of each scheduling decision, allowing the system to iteratively refine and select the最优 solution with high precision
Solution Approach 2:
The patent combines ACO's probabilistic solution exploration capability with entropy-based cost calculation's precise evaluation capability. This composite approach creates a hybrid optimization system that maintains the adaptability of ACO while adding the measurement precision of entropy analysis, resulting in both versatile solution exploration and precise selection
Data Source
AI summary
A method for designing an integrated circuit is described. The method comprises converting behavioral descriptions of the integrated circuit to register transfer level (RTL) descriptions. The method comprises at least one of the behavioral descriptions including frame synthesis with an input frame and a corresponding output frame. In one embodiment, the method further comprises providing at least two solutions for performing partial and complete operations for simulations as hardware component combinations, associating each solution with a cost, and selecting the solution with the lowest cost as the hardware component combination for a final design of the integrated circuit.