Entropy Encoder Circuit Layout for Faster Hardware Decoding
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Solution Overview
Problem
Current memory systems with non-volatile memory, such as SSDs, face challenges in increasing the processing speeds of encoding and decoding operations due to limitations in hardware implementation of arithmetic encoding and decoding methods.
Innovation Solution
The implementation of an entropy code encoder and decoder with specific arithmetic circuits and configurations, including registers, comparators, and arithmetic units, that perform calculations such as division, remainder calculations, and bit-shifting to enhance processing speeds by optimizing the operations of the entropy encoding and decoding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If arithmetic encoding and decoding methods are implemented in hardware, then processing speeds should increase, but circuit complexity increases and operating frequency decreases
Solution Approach 1:
The encoder is divided into multiple independent arithmetic circuits (first arithmetic circuit for frequency calculation, second arithmetic circuit for cumulative distribution, third arithmetic circuit for division, fourth arithmetic circuit for remainder, fifth arithmetic circuit for bit-shifting). Each circuit handles a specific computational task, allowing parallel operation and reducing overall circuit complexity while maintaining high processing speed.
Solution Approach 2:
The patent transitions from sequential software-based arithmetic operations to parallel hardware circuit implementation, adding a spatial dimension to computation. Multiple arithmetic circuits operate simultaneously in different hardware dimensions rather than sequentially in software, dramatically increasing processing speed while keeping individual circuit blocks manageable in size.
2Productivity
If complex arithmetic operations are performed in hardware, then encoding efficiency improves, but circuit size increases
Solution Approach 1:
Complex arithmetic operations are segmented into specialized circuits: first arithmetic circuit for appearance frequency, second for cumulative distribution, third for division, fourth for remainder calculations, and fifth for bit-shifting. This segmentation allows each circuit to be optimized for its specific function, reducing the area required for each individual circuit while achieving high encoding efficiency through parallel operation.
Solution Approach 2:
Each arithmetic circuit is designed with local optimization for its specific computational task. The third arithmetic circuit is optimized for division operations, the fourth for remainder calculations, and the fifth for bit-shifting operations. This local quality optimization ensures that each circuit block uses minimal area while performing its specific function efficiently, contributing to overall compact design.
Data Source
AI summary
An entropy code encoder includes a register and first, second, third, and fourth arithmetic circuits. The first arithmetic circuit is configured to output, based on an input symbol, a first value corresponding to an appearance frequency of the input symbol and a second value corresponding to a cumulative distribution of the first value. The second arithmetic circuit is configured to output a third value corresponding to division of a value of bits in the register by the first value. The third arithmetic circuit is configured to output a fourth value obtained by adding the second value to a bit-shifted value of the third value, to update a value in the register. The fourth arithmetic circuit is configured to compare the value of upper bits in the register and the first value and output a value of lower bits in the register as a compressed data stream.