Entropy Encoding Compression for FPGA-Friendly Hardware
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Solution Overview
Problem
Existing data compression techniques, such as those using Asymmetric Numeral Systems (ANS), are not optimized for hardware-friendly implementations like Field Programmable Gate Arrays (FPGA) or Application Specific Integrated Circuits (ASIC), requiring a more efficient lossless compression method suitable for these platforms.
Innovation Solution
A lossless compression method using entropy encoding that involves generating occurrence and cumulative occurrence tables to dynamically determine shifts for right-shifting states, allowing for efficient encoding and decoding of data blocks, specifically designed for hardware-friendly implementations by optimizing table storage and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If existing ANS implementations are used, then compression ratio is improved, but hardware implementation complexity increases
Solution Approach 1:
The patent segments the encoding process into distinct hardware modules: a frequency counter for generating occurrence tables, a cumulative sum unit for processing, and an encoder core for compression. This modular segmentation allows each component to be independently optimized for hardware implementation, reducing overall implementation complexity while maintaining compression effectiveness.
Solution Approach 2:
The patent performs preliminary computation of occurrence tables and cumulative sum tables before the actual encoding process. By pre-calculating these frequency-based structures, the hardware encoder can operate more efficiently without performing complex calculations during real-time compression, thus reducing hardware complexity.
2Adaptability or versatility
If general-purpose CPU is used, then processing flexibility is improved, but processing speed decreases
Solution Approach 1:
The patent replaces the software-based entropy encoding process on general-purpose CPUs with a dedicated hardware encoder implemented in FPGA or ASIC. This substitution of mechanical/software processing with specialized hardware circuitry dramatically increases processing speed while maintaining the flexibility of the entropy encoding algorithm through configurable design.
3Speed
If hardware-friendly implementation is achieved, then processing speed is improved, but memory requirements increase
Solution Approach 1:
The patent optimizes the memory requirements by carefully selecting the precision parameters for the occurrence tables and cumulative sum tables. By adjusting these parameters to match the specific application's data characteristics, the hardware encoder achieves fast processing speeds while minimizing the memory resources required for table storage.
Data Source
AI summary
Systems, apparatus and methods are provided for compressing data and decompressing compressed data. A method may comprise receiving an input data block to be compressed, generating a number of occurrences table and a cumulative occurrences table for distinct symbols in the input data block, for each symbol in the input data block, based on the number of occurrences table and the cumulative occurrences table, dynamically obtaining a number of shifts for right-shifting a current state “x” to encode a current symbol, outputting right-shifted bits to encoded data and obtaining a next state “x” and obtaining a final state “X” from a last state “x” generated in a final loop.