Entropy Encoding Pipeline for High-Throughput Data Compression

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Solution Overview

Problem

Current data compression methods for semiconductor memory systems, especially in data centers, face challenges in achieving high-throughput compression due to limitations in software-based algorithms, which are not suitable for high-bandwidth applications, necessitating the development of hardware-based compression solutions to enhance storage capacity and reduce data bandwidth.

Innovation Solution

The implementation of a hardware compression engine pipeline that incorporates dictionary-based and entropy compression techniques, with adaptive codebook selection and dynamic compression parameter control, to efficiently compress data across varying throughput and system conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If software-based compression algorithms are used, then compression capability is provided, but throughput is limited to hundreds of MB/s which is not suitable for high-bandwidth data center applications

Engineering Contradiction:
ImprovethroughputVSAvoidcompression engine complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces software-based compression algorithms with a hardware-based compression engine implemented as dedicated circuitry. This substitution of mechanical/software processing with hardware implementation enables throughput in the GB/s range, overcoming the MB/s limitation of software-based approaches while providing the necessary compression capability for high-bandwidth data center applications.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If hardware-based compression accelerators are implemented, then high throughput is achieved, but device complexity and circuit design challenges increase

Engineering Contradiction:
Improvedata compression throughputVSAvoidhardware compression engine complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The compression engine is divided into multiple independent processing pipelines, each capable of handling compression for different data streams simultaneously. This segmentation allows the system to achieve high aggregate throughput by parallelizing compression operations across multiple pipelines, while each individual pipeline maintains manageable complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The compression engine incorporates dynamic parameter adjustment capabilities where compression parameters can be adapted based on input data characteristics and system conditions. This dynamic behavior allows the hardware engine to optimize compression performance for different data types while maintaining high throughput, reducing the need for overly complex fixed-logic designs.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If dedicated hardware compression circuits are provided, then compression capability is enhanced, but cost and device complexity increase

Engineering Contradiction:
Improvecompression adaptabilityVSAvoidcompression circuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The hardware compression engine is designed with universal components that can handle multiple compression algorithms and data types through configurable parameters. Rather than implementing separate dedicated circuits for each compression method, the engine uses a unified architecture that can be dynamically configured, reducing overall device complexity while maintaining high adaptability to different compression requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11914862B2Data compression with entropy encoding
Publication Date: 2024.02.27 SANDISK TECHNOLOGIES LLC
  • US11914862B2 patent drawing
  • US11914862B2 patent drawing
  • US11914862B2 patent drawing

AI summary

An apparatus includes a first encoder circuit configured to compress a block of data using dictionary based compression and a second encoder circuit connected to the first encoder circuit to receive the compressed block of data from the first encoder circuit. The second encoder circuit is configured to further compress the compressed block of data according to a codebook. The codebook is based on a distribution of data of a prior block of data or a distribution of data of a portion of the block of data that is less than the block of data. The operation of the second encoder circuit overlaps with the operation of the first encoder circuit to achieve high throughput and avoid the need for a large block of memory (e.g., SRAM) to occupy the data in flight until the second encoder circuit can start.