Entropy Encoder Probability Circuit Without FPU Division
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Solution Overview
Problem
Current data compression methods, particularly for lossless compression, require complex calculations and dedicated circuitry for computing normalized probabilities, which can be power-intensive and occupy significant silicon space, limiting their efficiency and scalability in cloud and communication service providers' networks.
Innovation Solution
The proposed solution approximates normalized probability calculations using basic arithmetic components like adders, subtractors, and shifters, eliminating the need for a Floating Point Unit (FPU) and reducing circuitry, while maintaining accuracy compatible with Zstandard specifications, thus enabling more efficient data compression without the need for FPU-based divisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If FPU-based normalized probability calculation is used, then compression accuracy is improved, but hardware complexity and power consumption increase
Solution Approach 1:
The patent replaces the expensive FPU with inexpensive basic arithmetic components (adders, subtractors, shifters) that can be easily implemented in hardware. These simpler components perform the necessary normalized probability calculations without requiring complex floating-point division units, thereby reducing hardware complexity while maintaining sufficient compression accuracy for lossless data compression.
Solution Approach 2:
The patent changes the computational approach from floating-point division to fixed-point arithmetic using basic operations. By transforming the calculation method and using integer-based arithmetic with shift operations instead of floating-point division, the system achieves the same functional result with significantly reduced hardware requirements and lower power consumption.
2Measurement precision
If FPU-based normalized probability calculation is used, then compression accuracy is improved, but power consumption increases
Solution Approach 1:
The patent replaces the power-intensive FPU with low-power basic arithmetic components. Adders, subtractors, and shifters consume significantly less power than floating-point division units, enabling the system to maintain compression accuracy while dramatically reducing power consumption for data center and network operations.
Solution Approach 2:
The patent substitutes the mechanical/electrical complex FPU system with a simpler arithmetic system based on basic logic gates and arithmetic components. This substitution eliminates the need for complex floating-point circuitry while achieving the same computational goal through simpler, more energy-efficient operations.
3Measurement precision
If FPU-based normalized probability calculation is used, then compression accuracy is improved, but silicon die size increases
Solution Approach 1:
The patent replaces the large FPU with compact basic arithmetic components that occupy minimal silicon real estate. The adders, subtractors, and shifters required for normalized probability calculation can be implemented in a fraction of the space needed for an FPU, enabling higher integration density in data center hardware and network devices.
Solution Approach 2:
The patent breaks down the normalized probability calculation into discrete basic arithmetic operations that can be independently implemented and optimized. By segmenting the computation into separate adder, subtractor, and shifter units, the system achieves the same result with modular, space-efficient hardware that can be tightly integrated on the silicon die.
Data Source
AI summary
Examples described herein relate to an apparatus comprising a central processing unit (CPU) and an encoding accelerator coupled to the CPU, the encoding accelerator comprising an entropy encoder to determine normalized probability of occurrence of a symbol in a set of characters using a normalized probability approximation circuitry, wherein the normalized probability approximation circuitry is to output the normalized probability of occurrence of a symbol in a set of characters for lossless compression. In some examples, the normalized probability approximation circuitry includes a shifter, adder, subtractor, or a comparator. In some examples, the normalized probability approximation circuitry is to determine normalized probability by performance of non-power of 2 division without computation by a Floating Point Unit (FPU). In some examples, the normalized probability approximation circuitry is to round the normalized probability to a decimal.