Envelope Detection Circuit With Self-Biasing RF Edge Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing envelope detection circuits for low-power applications, such as wireless sensor nodes, face challenges including complex circuit arrangements, sensitivity to process, voltage, and temperature (PVT) variations, mismatch issues, and the inability to detect both rising and falling edges of RF-modulated signals effectively, which affects noise bandwidth and requires complex calibration.
Innovation Solution
An envelope detection circuit with a common-gate input stage and a negative feedback network for self-biasing, incorporating a source follower and a capacitor for filtering, and a cascoded common-gate circuit arrangement to facilitate edge detection and AC coupling, allowing operation at higher RF frequencies and robustness against PVT variations without complex calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex circuit arrangements are used to set the DC operating point, then detection precision is improved, but device complexity increases
Solution Approach 1:
The patent employs self-biasing circuit arrangements where the circuit automatically sets its own DC operating point without requiring external complex biasing circuits. The detection circuit includes transistors configured to automatically establish stable operating conditions through their inherent electrical characteristics, eliminating the need for additional complex biasing components while maintaining detection precision.
2Measurement precision
If complex calibration procedures are implemented, then measurement precision is improved, but ease of operation deteriorates
Solution Approach 1:
The detection circuit is designed with automatic self-biasing capabilities that eliminate the need for manual calibration procedures. The circuit automatically adapts to process, voltage, and temperature variations through its inherent design, allowing operation without complex calibration steps while maintaining high measurement precision across different operating conditions.
3Measurement precision
If differential circuit architecture is used, then detection precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for complex differential circuit architectures by using a simplified single-ended detection circuit design. The invention achieves detection precision comparable to or better than differential designs by removing unnecessary complexity through innovative use of self-biasing transistor configurations that inherently reject common-mode disturbances without requiring matched differential pairs.
4Ease of manufacture
If common-source input stage is used, then ease of manufacture is improved, but speed deteriorates
Solution Approach 1:
The patent transitions from common-source to common-gate input stage configuration, changing the circuit topology parameter to achieve higher operating speeds. The common-gate configuration reduces input capacitance and improves bandwidth, enabling the circuit to operate at higher RF frequencies while maintaining ease of manufacture through standard transistor implementations available in typical CMOS processes.
Data Source
Figure 1~3
Figure 4~6
Figure 7~8
AI summary
An envelope detection circuit (20) is described. The circuit (20) comprises: - an input node (204) configured to receive an input analog signal (VRF) resulting from amplitude modulation of a radio-frequency carrier by a digital signal, - an output node (208) configured to provide an output signal (Vout) indicative of rising and falling edges of an envelope of said input analog signal (VRF) received, said rising and falling edges being indicative of rising and falling edges of said digital signal, and - a first current path between a power supply node (Vdd) and the input node (204), the first current path comprising at least one first transistor (M1) having the current path therethrough coupled between the input node (204) and a first bias source (G1, Ibias), the first bias source (G1, Ibias) coupled between the at least one first transistor (M1) and the power supply node (Vdd). The output node (208) is coupled to a node in the first current path intermediate the at least one first transistor (M1) and the first bias source (G1), and a control terminal of the at least one first transistor (M1) is coupled to the output node (208) via a feedback network (R, C).