Envelope Detector Bias Linearization for Wide RF Dynamic Range
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Solution Overview
Problem
Existing envelope detectors (EDs) in cellular transmitters face challenges in achieving the required linear range and accuracy for proper calibration and power detection, often necessitating external envelope detection and excessive factory calibration, which increases costs and complexity.
Innovation Solution
An enhanced envelope detector core with a voltage-mode configuration using parallel detection transistors biased in the subthreshold region, coupled with a linearizer circuit and a specialized class-AB amplifier, which adjusts bias currents based on differential outputs to maintain linearity across a wide voltage amplitude range, eliminating the need for external detection and reducing calibration points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If detection transistors are biased in subthreshold region to improve linearity, then linear range is improved, but detection sensitivity deteriorates
Solution Approach 1:
The patent implements dynamic bias control by using a bias control circuit that adjusts the bias current of detection transistors based on the input signal amplitude. The bias current transitions from a first bias value at low signal levels to a second bias value at high signal levels, enabling the system to maintain optimal performance across different operating conditions and resolve the contradiction between linearity and sensitivity.
Solution Approach 2:
The patent changes the operating parameters of detection transistors dynamically by adjusting bias current based on signal amplitude. At low signal levels, a higher bias current maintains detection sensitivity, while at high signal levels, a lower bias current maintains linearity. This parameter adaptation resolves the contradiction between the two performance requirements.
2Manufacturing precision
If external envelope detector is used to achieve required linear range, then linear range is improved, but device complexity increases
Solution Approach 1:
The patent merges the envelope detection function with the existing voltage amplifier by integrating detection transistors into the amplifier circuit. The detection transistors are coupled to the amplifier output, allowing the same circuit to perform both amplification and envelope detection functions, thereby eliminating the need for a separate external envelope detector and reducing overall device complexity.
Solution Approach 2:
The integrated circuit performs multiple functions: it acts as both a voltage amplifier and an envelope detector. The detection transistors extract envelope information from the amplified signal, enabling the single circuit to fulfill both amplification and detection roles, thus reducing the number of external components needed.
3Measurement precision
If factory open loop power calibration is performed to achieve accuracy, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent implements self-calibration through a bias control circuit that automatically adjusts detection transistor bias based on real-time signal amplitude measurements. The system monitors its own performance and dynamically optimizes its operating parameters without requiring external calibration equipment or time-consuming factory calibration procedures, thereby achieving accurate measurements while eliminating calibration time losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a linear range of up to 60 dB, reduces power consumption, and enhances calibration capabilities, making the technology more cost-effective and adaptable for various communication standards while maintaining accuracy and efficiency.
Implementation Method 1
a voltage-mode envelope detector (ED) core including a first and a second pair of parallel detection transistors for detecting a voltage envelope of a radio frequency (RF) signal input; where the detection transistors are configured to be biased in a subthreshold region of operation
Implementation Method 2
a linearizer circuit configured with a differential amplifier connected to the differential positive and negative ED outputs, the linearizer circuit configured to generate the bias voltage as proportional to a difference between the positive and negative ED outputs, to enhance a linear range of the ED while maintaining the detection transistors in subthreshold regions despite a widened voltage amplitude range
Implementation Method 3
a final voltage amplifier of the multiple voltage amplifiers drives the ED core and comprises a class-AB RF amplifier configured to operate within a full linear voltage range of the ED core
Data Source
Figure 1~2B
Figure 3A~3C
Figure 4~5
AI summary
An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED.